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47579cf390
This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
1.5 KiB
LLVM
56 lines
1.5 KiB
LLVM
; RUN: llc < %s -enable-misched -pre-RA-sched=source -scheditins=false \
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; RUN: -disable-ifcvt-triangle-false -disable-post-ra | FileCheck %s
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;
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-bgq-linux"
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; %val1 is a load live out of %entry. It should be hoisted
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; above the add.
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; CHECK: testload:
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; CHECK: %entry
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; CHECK: lwz
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; CHECK: addi
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; CHECK: bne
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; CHECK: %true
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define i32 @testload(i32 *%ptr, i32 %sumin) {
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entry:
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%sum1 = add i32 %sumin, 1
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%val1 = load i32* %ptr
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%p = icmp eq i32 %sumin, 0
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br i1 %p, label %true, label %end
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true:
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%sum2 = add i32 %sum1, 1
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%ptr2 = getelementptr i32* %ptr, i32 1
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%val = load i32* %ptr2
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%val2 = add i32 %val1, %val
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br label %end
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end:
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%valmerge = phi i32 [ %val1, %entry], [ %val2, %true ]
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%summerge = phi i32 [ %sum1, %entry], [ %sum2, %true ]
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%sumout = add i32 %valmerge, %summerge
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ret i32 %sumout
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}
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; The prefetch gets a default latency of 3 cycles and should be hoisted
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; above the add.
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;
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; CHECK: testprefetch:
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; CHECK: %entry
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; CHECK: dcbt
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; CHECK: addi
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; CHECK: blr
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define i32 @testprefetch(i8 *%ptr, i32 %i) {
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entry:
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%val1 = add i32 %i, 1
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
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%p = icmp eq i32 %i, 0
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br i1 %p, label %true, label %end
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true:
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%val2 = add i32 %val1, 1
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br label %end
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end:
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%valmerge = phi i32 [ %val1, %entry], [ %val2, %true ]
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ret i32 %valmerge
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}
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declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
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