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https://github.com/c64scene-ar/llvm-6502.git
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bbbe413846
// C - zext(bool) -> bool ? C - 1 : C
if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1))
if (ZI->getSrcTy()->isIntegerTy(1))
return SelectInst::Create(ZI->getOperand(0), SubOne(C), C);
This ends up forming sext i1 instructions that codegen to terrible code. e.g.
int blah(_Bool x, _Bool y) {
return (x - y) + 1;
}
=>
movzbl %dil, %eax
movzbl %sil, %ecx
shll $31, %ecx
sarl $31, %ecx
leal 1(%rax,%rcx), %eax
ret
Without the rule, llvm now generates:
movzbl %sil, %ecx
movzbl %dil, %eax
incl %eax
subl %ecx, %eax
ret
It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-).
The transformation was done as part of Eli's r75531. He has given the ok to
remove it.
rdar://11748024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159230 91177308-0d34-0410-b5e6-96231b3b80d8
17 lines
432 B
LLVM
17 lines
432 B
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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; rdar://11748024
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define i32 @a(i1 zeroext %x, i1 zeroext %y) {
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entry:
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; CHECK: @a
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; CHECK: [[TMP1:%.*]] = zext i1 %y to i32
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; CHECK: [[TMP2:%.*]] = select i1 %x, i32 2, i32 1
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; CHECK-NEXT: sub i32 [[TMP2]], [[TMP1]]
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%conv = zext i1 %x to i32
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%conv3 = zext i1 %y to i32
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%conv3.neg = sub i32 0, %conv3
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%sub = add i32 %conv, 1
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%add = add i32 %sub, %conv3.neg
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ret i32 %add
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}
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