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shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8
186 lines
6.2 KiB
C++
186 lines
6.2 KiB
C++
//===---- HexagonFixupHwLoops.cpp - Fixup HW loops too far from LOOPn. ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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// The loop start address in the LOOPn instruction is encoded as a distance
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// from the LOOPn instruction itself. If the start address is too far from
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// the LOOPn instruction, the loop needs to be set up manually, i.e. via
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// direct transfers to SAn and LCn.
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// This pass will identify and convert such LOOPn instructions to a proper
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// form.
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/DenseMap.h"
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#include "Hexagon.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/PassSupport.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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namespace llvm {
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void initializeHexagonFixupHwLoopsPass(PassRegistry&);
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}
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namespace {
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struct HexagonFixupHwLoops : public MachineFunctionPass {
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public:
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static char ID;
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HexagonFixupHwLoops() : MachineFunctionPass(ID) {
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initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "Hexagon Hardware Loop Fixup";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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/// \brief Maximum distance between the loop instr and the basic block.
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/// Just an estimate.
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static const unsigned MAX_LOOP_DISTANCE = 200;
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/// \brief Check the offset between each loop instruction and
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/// the loop basic block to determine if we can use the LOOP instruction
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/// or if we need to set the LC/SA registers explicitly.
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bool fixupLoopInstrs(MachineFunction &MF);
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/// \brief Add the instruction to set the LC and SA registers explicitly.
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void convertLoopInstr(MachineFunction &MF,
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MachineBasicBlock::iterator &MII,
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RegScavenger &RS);
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};
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char HexagonFixupHwLoops::ID = 0;
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}
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INITIALIZE_PASS(HexagonFixupHwLoops, "hwloopsfixup",
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"Hexagon Hardware Loops Fixup", false, false)
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FunctionPass *llvm::createHexagonFixupHwLoops() {
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return new HexagonFixupHwLoops();
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}
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/// \brief Returns true if the instruction is a hardware loop instruction.
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static bool isHardwareLoop(const MachineInstr *MI) {
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return MI->getOpcode() == Hexagon::LOOP0_r ||
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MI->getOpcode() == Hexagon::LOOP0_i;
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}
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bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = fixupLoopInstrs(MF);
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return Changed;
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}
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/// \brief For Hexagon, if the loop label is to far from the
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/// loop instruction then we need to set the LC0 and SA0 registers
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/// explicitly instead of using LOOP(start,count). This function
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/// checks the distance, and generates register assignments if needed.
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///
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/// This function makes two passes over the basic blocks. The first
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/// pass computes the offset of the basic block from the start.
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/// The second pass checks all the loop instructions.
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bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {
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// Offset of the current instruction from the start.
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unsigned InstOffset = 0;
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// Map for each basic block to it's first instruction.
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DenseMap<MachineBasicBlock*, unsigned> BlockToInstOffset;
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// First pass - compute the offset of each basic block.
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for (MachineFunction::iterator MBB = MF.begin(), MBBe = MF.end();
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MBB != MBBe; ++MBB) {
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BlockToInstOffset[MBB] = InstOffset;
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InstOffset += (MBB->size() * 4);
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}
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// Second pass - check each loop instruction to see if it needs to
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// be converted.
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InstOffset = 0;
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bool Changed = false;
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RegScavenger RS;
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// Loop over all the basic blocks.
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for (MachineFunction::iterator MBB = MF.begin(), MBBe = MF.end();
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MBB != MBBe; ++MBB) {
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InstOffset = BlockToInstOffset[MBB];
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RS.enterBasicBlock(MBB);
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// Loop over all the instructions.
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MachineBasicBlock::iterator MIE = MBB->end();
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MachineBasicBlock::iterator MII = MBB->begin();
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while (MII != MIE) {
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if (isHardwareLoop(MII)) {
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RS.forward(MII);
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assert(MII->getOperand(0).isMBB() &&
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"Expect a basic block as loop operand");
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int Sub = InstOffset - BlockToInstOffset[MII->getOperand(0).getMBB()];
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unsigned Dist = Sub > 0 ? Sub : -Sub;
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if (Dist > MAX_LOOP_DISTANCE) {
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// Convert to explicity setting LC0 and SA0.
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convertLoopInstr(MF, MII, RS);
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MII = MBB->erase(MII);
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Changed = true;
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} else {
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++MII;
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}
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} else {
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++MII;
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}
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InstOffset += 4;
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}
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}
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return Changed;
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}
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/// \brief convert a loop instruction to a sequence of instructions that
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/// set the LC0 and SA0 register explicitly.
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void HexagonFixupHwLoops::convertLoopInstr(MachineFunction &MF,
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MachineBasicBlock::iterator &MII,
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RegScavenger &RS) {
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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MachineBasicBlock *MBB = MII->getParent();
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DebugLoc DL = MII->getDebugLoc();
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unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
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// First, set the LC0 with the trip count.
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if (MII->getOperand(1).isReg()) {
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// Trip count is a register
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BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
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.addReg(MII->getOperand(1).getReg());
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} else {
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// Trip count is an immediate.
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BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFRI), Scratch)
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.addImm(MII->getOperand(1).getImm());
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BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::LC0)
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.addReg(Scratch);
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}
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// Then, set the SA0 with the loop start address.
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BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
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.addMBB(MII->getOperand(0).getMBB());
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BuildMI(*MBB, MII, DL, TII->get(Hexagon::TFCR), Hexagon::SA0)
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.addReg(Scratch);
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}
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