mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-22 23:31:32 +00:00
8be6bbe5bf
priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
|---|---|---|
| .. | ||
| Alpha.h | ||
| Alpha.td | ||
| AlphaAsmPrinter.cpp | ||
| AlphaBranchSelector.cpp | ||
| AlphaCodeEmitter.cpp | ||
| AlphaInstrFormats.td | ||
| AlphaInstrInfo.cpp | ||
| AlphaInstrInfo.h | ||
| AlphaInstrInfo.td | ||
| AlphaISelDAGToDAG.cpp | ||
| AlphaISelLowering.cpp | ||
| AlphaISelLowering.h | ||
| AlphaJITInfo.cpp | ||
| AlphaJITInfo.h | ||
| AlphaLLRP.cpp | ||
| AlphaRegisterInfo.cpp | ||
| AlphaRegisterInfo.h | ||
| AlphaRegisterInfo.td | ||
| AlphaRelocations.h | ||
| AlphaSchedule.td | ||
| AlphaSubtarget.cpp | ||
| AlphaSubtarget.h | ||
| AlphaTargetAsmInfo.cpp | ||
| AlphaTargetAsmInfo.h | ||
| AlphaTargetMachine.cpp | ||
| AlphaTargetMachine.h | ||
| CMakeLists.txt | ||
| Makefile | ||
| README.txt | ||
*** add gcc builtins for alpha instructions *** custom expand byteswap into nifty extract/insert/mask byte/word/longword/quadword low/high sequences *** see if any of the extract/insert/mask operations can be added *** match more interesting things for cmovlbc cmovlbs (move if low bit clear/set) *** lower srem and urem remq(i,j): i - (j * divq(i,j)) if j != 0 remqu(i,j): i - (j * divqu(i,j)) if j != 0 reml(i,j): i - (j * divl(i,j)) if j != 0 remlu(i,j): i - (j * divlu(i,j)) if j != 0 *** add crazy vector instructions (MVI): (MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word PKWB, UNPKBW pack/unpack word to byte PKLB UNPKBL pack/unpack long to byte PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b)) cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions) this has some good examples for other operations that can be synthesised well from these rather meager vector ops (such as saturating add). http://www.alphalinux.org/docs/MVI-full.html