mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d99ce2f630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239370 91177308-0d34-0410-b5e6-96231b3b80d8
302 lines
9.5 KiB
C++
302 lines
9.5 KiB
C++
//===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an Hexagon MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonAsmPrinter.h"
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#include "Hexagon.h"
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#include "HexagonInstPrinter.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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#define GET_INSTRUCTION_NAME
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#include "HexagonGenAsmWriter.inc"
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HexagonAsmInstPrinter::HexagonAsmInstPrinter(MCInstPrinter *RawPrinter)
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: MCInstPrinter(*RawPrinter), RawPrinter(RawPrinter) {}
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void HexagonAsmInstPrinter::printInst(MCInst const *MI, raw_ostream &O,
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StringRef Annot,
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MCSubtargetInfo const &STI) {
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assert(HexagonMCInstrInfo::isBundle(*MI));
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assert(HexagonMCInstrInfo::bundleSize(*MI) <= HEXAGON_PACKET_SIZE);
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std::string Buffer;
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{
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raw_string_ostream TempStream(Buffer);
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RawPrinter->printInst(MI, TempStream, "", STI);
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}
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StringRef Contents(Buffer);
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auto PacketBundle = Contents.rsplit('\n');
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auto HeadTail = PacketBundle.first.split('\n');
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auto Preamble = "\t{\n\t\t";
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auto Separator = "";
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while(!HeadTail.first.empty()) {
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O << Separator;
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StringRef Inst;
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auto Duplex = HeadTail.first.split('\v');
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if(!Duplex.second.empty()){
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O << Duplex.first << "\n";
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Inst = Duplex.second;
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}
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else
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Inst = Duplex.first;
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O << Preamble;
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O << Inst;
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HeadTail = HeadTail.second.split('\n');
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Preamble = "";
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Separator = "\n\t\t";
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}
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O << "\n\t}" << PacketBundle.second;
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}
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void HexagonAsmInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
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RawPrinter->printRegName(O, RegNo);
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}
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// Return the minimum value that a constant extendable operand can have
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// without being extended.
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static int getMinValue(uint64_t TSFlags) {
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unsigned isSigned =
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(TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
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unsigned bits =
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(TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
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if (isSigned)
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return -1U << (bits - 1);
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return 0;
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}
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// Return the maximum value that a constant extendable operand can have
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// without being extended.
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static int getMaxValue(uint64_t TSFlags) {
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unsigned isSigned =
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(TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
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unsigned bits =
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(TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
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if (isSigned)
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return ~(-1U << (bits - 1));
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return ~(-1U << bits);
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}
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// Return true if the instruction must be extended.
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static bool isExtended(uint64_t TSFlags) {
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return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
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}
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// Currently just used in an assert statement
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static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;
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// Return true if the instruction may be extended based on the operand value.
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static bool isExtendable(uint64_t TSFlags) {
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return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
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}
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StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {
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return MII.getName(Opcode);
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}
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void HexagonInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void HexagonInstPrinter::setExtender(MCInst const &MCI) {
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HasExtender = HexagonMCInstrInfo::isImmext(MCI);
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}
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void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &OS,
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StringRef Annot,
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MCSubtargetInfo const &STI) {
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assert(HexagonMCInstrInfo::isBundle(*MI));
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assert(HexagonMCInstrInfo::bundleSize(*MI) <= HEXAGON_PACKET_SIZE);
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HasExtender = false;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MI)) {
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MCInst const &MCI = *I.getInst();
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if (HexagonMCInstrInfo::isDuplex(MII, MCI)) {
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printInstruction(MCI.getOperand(1).getInst(), OS);
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OS << '\v';
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HasExtender = false;
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printInstruction(MCI.getOperand(0).getInst(), OS);
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} else
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printInstruction(&MCI, OS);
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setExtender(MCI);
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OS << "\n";
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}
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auto Separator = "";
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if (HexagonMCInstrInfo::isInnerLoop(*MI)) {
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OS << Separator;
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Separator = " ";
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MCInst ME;
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ME.setOpcode(Hexagon::ENDLOOP0);
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printInstruction(&ME, OS);
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}
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if (HexagonMCInstrInfo::isOuterLoop(*MI)) {
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OS << Separator;
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Separator = " ";
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MCInst ME;
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ME.setOpcode(Hexagon::ENDLOOP1);
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printInstruction(&ME, OS);
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}
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}
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void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand& MO = MI->getOperand(OpNo);
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if (MO.isReg()) {
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printRegName(O, MO.getReg());
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} else if(MO.isExpr()) {
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MO.getExpr()->print(O, &MAI);
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} else if(MO.isImm()) {
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printImmOperand(MI, OpNo, O);
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} else {
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llvm_unreachable("Unknown operand");
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}
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}
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void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand& MO = MI->getOperand(OpNo);
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if(MO.isExpr()) {
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MO.getExpr()->print(O, &MAI);
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} else if(MO.isImm()) {
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O << MI->getOperand(OpNo).getImm();
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} else {
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llvm_unreachable("Unknown operand");
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}
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}
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void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand &MO = MI->getOperand(OpNo);
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const MCInstrDesc &MII = getMII().get(MI->getOpcode());
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assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&
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"Expecting an extendable operand");
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if (MO.isExpr() || isExtended(MII.TSFlags)) {
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O << "#";
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} else if (MO.isImm()) {
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int ImmValue = MO.getImm();
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if (ImmValue < getMinValue(MII.TSFlags) ||
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ImmValue > getMaxValue(MII.TSFlags))
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O << "#";
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}
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printOperand(MI, OpNo, O);
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}
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void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
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unsigned OpNo, raw_ostream &O) const {
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O << MI->getOperand(OpNo).getImm();
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}
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void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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O << -MI->getOperand(OpNo).getImm();
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}
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void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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O << -1;
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}
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void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand& MO0 = MI->getOperand(OpNo);
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const MCOperand& MO1 = MI->getOperand(OpNo + 1);
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printRegName(O, MO0.getReg());
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O << " + #" << MO1.getImm();
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}
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void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand& MO0 = MI->getOperand(OpNo);
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const MCOperand& MO1 = MI->getOperand(OpNo + 1);
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printRegName(O, MO0.getReg());
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O << ", #" << MO1.getImm();
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}
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void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
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printOperand(MI, OpNo, O);
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}
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void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
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printOperand(MI, OpNo, O);
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}
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void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
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printOperand(MI, OpNo, O);
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}
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void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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// Branches can take an immediate operand. This is used by the branch
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// selection pass to print $+8, an eight byte displacement from the PC.
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llvm_unreachable("Unknown branch operand.");
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}
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void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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}
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void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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}
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void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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}
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void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, bool hi) const {
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assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");
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O << '#' << (hi ? "HI" : "LO") << "(#";
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printOperand(MI, OpNo, O);
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O << ')';
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}
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void HexagonInstPrinter::printExtBrtarget(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) const {
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const MCOperand &MO = MI->getOperand(OpNo);
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const MCInstrDesc &MII = getMII().get(MI->getOpcode());
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assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&
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"Expecting an extendable operand");
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if (MO.isExpr() || isExtended(MII.TSFlags)) {
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O << "##";
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}
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printOperand(MI, OpNo, O);
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}
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