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https://github.com/c64scene-ar/llvm-6502.git
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d15cd2752f
the loop, and in both cases. In the first case, it is a VReg that is a constant so it may be actually converted to a constant. In the second case, it is already a constant, but then if it doesn't change its type (e.g. to become a register and have the value loaded from memory if it is too large to live in its instruction field), we must change the opcode BEFORE the 'continue', otherwise we miss the opportunity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6602 91177308-0d34-0410-b5e6-96231b3b80d8
286 lines
11 KiB
C++
286 lines
11 KiB
C++
//===-- InstrSelectionSupport.cpp -----------------------------------------===//
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//
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// Target-independent instruction selection code. See SparcInstrSelection.cpp
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// for usage.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineInstrAnnot.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/InstrForest.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/DerivedTypes.h"
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#include "../../Target/Sparc/SparcInstrSelectionSupport.h"
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using std::vector;
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//*************************** Local Functions ******************************/
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// Generate code to load the constant into a TmpInstruction (virtual reg) and
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// returns the virtual register.
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//
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static TmpInstruction*
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InsertCodeToLoadConstant(Function *F,
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Value* opValue,
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Instruction* vmInstr,
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vector<MachineInstr*>& loadConstVec,
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TargetMachine& target)
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{
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// Create a tmp virtual register to hold the constant.
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MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
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TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
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target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
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loadConstVec, mcfi);
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// Record the mapping from the tmp VM instruction to machine instruction.
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// Do this for all machine instructions that were not mapped to any
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// other temp values created by
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// tmpReg->addMachineInstruction(loadConstVec.back());
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return tmpReg;
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(int64_t intValue,
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bool isSigned,
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MachineOpCode opCode,
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const TargetMachine& target,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
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getMachineRegNum = 0;
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getImmedValue = 0;
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if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
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{
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opType = isSigned? MachineOperand::MO_SignExtendedImmed
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: MachineOperand::MO_UnextendedImmed;
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getImmedValue = intValue;
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}
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else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
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{
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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}
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return opType;
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(Value* val,
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MachineOpCode opCode,
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const TargetMachine& target,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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getMachineRegNum = 0;
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getImmedValue = 0;
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// To use reg or immed, constant needs to be integer, bool, or a NULL pointer
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Constant *CPV = dyn_cast<Constant>(val);
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if (CPV == NULL ||
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(! CPV->getType()->isIntegral() &&
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! (isa<PointerType>(CPV->getType()) && CPV->isNullValue())))
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return MachineOperand::MO_VirtualRegister;
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// Now get the constant value and check if it fits in the IMMED field.
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// Take advantage of the fact that the max unsigned value will rarely
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// fit into any IMMED field and ignore that case (i.e., cast smaller
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// unsigned constants to signed).
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//
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int64_t intValue;
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if (isa<PointerType>(CPV->getType()))
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intValue = 0; // We checked above that it is NULL
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else if (ConstantBool* CB = dyn_cast<ConstantBool>(CPV))
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intValue = (int64_t) CB->getValue();
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else if (CPV->getType()->isSigned())
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intValue = cast<ConstantSInt>(CPV)->getValue();
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else
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{ // get the int value and sign-extend if original was less than 64 bits
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intValue = (int64_t) cast<ConstantUInt>(CPV)->getValue();
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switch(CPV->getType()->getPrimitiveID())
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{
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case Type::UByteTyID: intValue = (int64_t) (int8_t) intValue; break;
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case Type::UShortTyID: intValue = (int64_t) (short) intValue; break;
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case Type::UIntTyID: intValue = (int64_t) (int) intValue; break;
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default: break;
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}
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}
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return ChooseRegOrImmed(intValue, CPV->getType()->isSigned(),
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opCode, target, canUseImmed,
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getMachineRegNum, getImmedValue);
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}
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//---------------------------------------------------------------------------
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// Function: FixConstantOperandsForInstr
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//
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// Purpose:
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// Special handling for constant operands of a machine instruction
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// -- if the constant is 0, use the hardwired 0 register, if any;
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// -- if the constant fits in the IMMEDIATE field, use that field;
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// -- else create instructions to put the constant into a register, either
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// directly or by loading explicitly from the constant pool.
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//
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// In the first 2 cases, the operand of `minstr' is modified in place.
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// Returns a vector of machine instructions generated for operands that
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// fall under case 3; these must be inserted before `minstr'.
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//---------------------------------------------------------------------------
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vector<MachineInstr*>
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FixConstantOperandsForInstr(Instruction* vmInstr,
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MachineInstr* minstr,
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TargetMachine& target)
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{
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vector<MachineInstr*> MVec;
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MachineOpCode opCode = minstr->getOpCode();
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const TargetInstrInfo& instrInfo = target.getInstrInfo();
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int resultPos = instrInfo.getResultPos(opCode);
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int immedPos = instrInfo.getImmedConstantPos(opCode);
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Function *F = vmInstr->getParent()->getParent();
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for (unsigned op=0; op < minstr->getNumOperands(); op++)
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{
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const MachineOperand& mop = minstr->getOperand(op);
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// Skip the result position, preallocated machine registers, or operands
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// that cannot be constants (CC regs or PC-relative displacements)
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if (resultPos == (int)op ||
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mop.getType() == MachineOperand::MO_MachineRegister ||
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mop.getType() == MachineOperand::MO_CCRegister ||
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mop.getType() == MachineOperand::MO_PCRelativeDisp)
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continue;
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bool constantThatMustBeLoaded = false;
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unsigned int machineRegNum = 0;
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int64_t immedValue = 0;
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Value* opValue = NULL;
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MachineOperand::MachineOperandType opType =
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MachineOperand::MO_VirtualRegister;
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// Operand may be a virtual register or a compile-time constant
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if (mop.getType() == MachineOperand::MO_VirtualRegister)
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{
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assert(mop.getVRegValue() != NULL);
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opValue = mop.getVRegValue();
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if (Constant *opConst = dyn_cast<Constant>(opValue)) {
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opType = ChooseRegOrImmed(opConst, opCode, target,
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(immedPos == (int)op), machineRegNum,
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immedValue);
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if (opType == MachineOperand::MO_VirtualRegister)
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constantThatMustBeLoaded = true;
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else {
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// The optype has changed from being a register to an immediate
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// This means we need to change the opcode, e.g. ADDr -> ADDi
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unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
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minstr->setOpcode(newOpcode);
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}
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}
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}
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else
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{
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assert(mop.isImmediate());
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bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
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// Bit-selection flags indicate an instruction that is extracting
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// bits from its operand so ignore this even if it is a big constant.
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if (mop.opHiBits32() || mop.opLoBits32() ||
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mop.opHiBits64() || mop.opLoBits64())
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continue;
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opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
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opCode, target, (immedPos == (int)op),
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machineRegNum, immedValue);
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if (opType == MachineOperand::MO_SignExtendedImmed) {
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// The optype is an immediate value
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// This means we need to change the opcode, e.g. ADDr -> ADDi
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unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
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minstr->setOpcode(newOpcode);
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}
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if (opType == mop.getType())
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continue; // no change: this is the most common case
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if (opType == MachineOperand::MO_VirtualRegister)
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{
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constantThatMustBeLoaded = true;
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opValue = isSigned
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? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
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: (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
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}
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}
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if (opType == MachineOperand::MO_MachineRegister)
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minstr->SetMachineOperandReg(op, machineRegNum);
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else if (opType == MachineOperand::MO_SignExtendedImmed ||
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opType == MachineOperand::MO_UnextendedImmed) {
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minstr->SetMachineOperandConst(op, opType, immedValue);
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} else if (constantThatMustBeLoaded ||
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(opValue && isa<GlobalValue>(opValue)))
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{ // opValue is a constant that must be explicitly loaded into a reg
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assert(opValue);
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TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
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MVec, target);
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minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
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tmpReg);
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}
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}
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// Also, check for implicit operands used by the machine instruction
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// (no need to check those defined since they cannot be constants).
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// These include:
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// -- arguments to a Call
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// -- return value of a Return
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// Any such operand that is a constant value needs to be fixed also.
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// The current instructions with implicit refs (viz., Call and Return)
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// have no immediate fields, so the constant always needs to be loaded
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// into a register.
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//
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bool isCall = instrInfo.isCall(opCode);
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unsigned lastCallArgNum = 0; // unused if not a call
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CallArgsDescriptor* argDesc = NULL; // unused if not a call
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if (isCall)
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argDesc = CallArgsDescriptor::get(minstr);
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for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
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if (isa<Constant>(minstr->getImplicitRef(i)) ||
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isa<GlobalValue>(minstr->getImplicitRef(i)))
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{
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Value* oldVal = minstr->getImplicitRef(i);
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TmpInstruction* tmpReg =
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InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
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minstr->setImplicitRef(i, tmpReg);
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if (isCall)
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{ // find and replace the argument in the CallArgsDescriptor
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unsigned i=lastCallArgNum;
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while (argDesc->getArgInfo(i).getArgVal() != oldVal)
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++i;
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assert(i < argDesc->getNumArgs() &&
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"Constant operands to a call *must* be in the arg list");
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lastCallArgNum = i;
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argDesc->getArgInfo(i).replaceArgVal(tmpReg);
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}
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}
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return MVec;
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}
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