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call arguments and return values: Now all copy operations before and after a call are generated during selection instead of during register allocation. The values are copied to virtual registers (or to the stack), but in the former case these operands are marked with the correct physical registers according to the calling convention. Although this complicates scheduling and does not work well with live range analysis, it simplifies the machine-dependent part of register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6465 91177308-0d34-0410-b5e6-96231b3b80d8
409 lines
15 KiB
C++
409 lines
15 KiB
C++
//===-- LiveRangeInfo.cpp -------------------------------------------------===//
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//
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// Live range construction for coloring-based register allocation for LLVM.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveRangeInfo.h"
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#include "RegAllocCommon.h"
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#include "RegClass.h"
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#include "llvm/CodeGen/IGNode.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Function.h"
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#include "Support/SetOperations.h"
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using std::cerr;
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unsigned LiveRange::getRegClassID() const { return getRegClass()->getID(); }
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LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
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std::vector<RegClass *> &RCL)
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: Meth(F), TM(tm), RegClassList(RCL), MRI(tm.getRegInfo()) { }
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LiveRangeInfo::~LiveRangeInfo() {
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for (LiveRangeMapType::iterator MI = LiveRangeMap.begin();
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MI != LiveRangeMap.end(); ++MI) {
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if (MI->first && MI->second) {
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LiveRange *LR = MI->second;
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// we need to be careful in deleting LiveRanges in LiveRangeMap
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// since two/more Values in the live range map can point to the same
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// live range. We have to make the other entries NULL when we delete
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// a live range.
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for (LiveRange::iterator LI = LR->begin(); LI != LR->end(); ++LI)
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LiveRangeMap[*LI] = 0;
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delete LR;
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}
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}
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}
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//---------------------------------------------------------------------------
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// union two live ranges into one. The 2nd LR is deleted. Used for coalescing.
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// Note: the caller must make sure that L1 and L2 are distinct and both
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// LRs don't have suggested colors
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//---------------------------------------------------------------------------
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void LiveRangeInfo::unionAndUpdateLRs(LiveRange *L1, LiveRange *L2) {
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assert(L1 != L2 && (!L1->hasSuggestedColor() || !L2->hasSuggestedColor()));
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assert(! (L1->hasColor() && L2->hasColor()) ||
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L1->getColor() == L2->getColor());
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set_union(*L1, *L2); // add elements of L2 to L1
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for(ValueSet::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) {
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//assert(( L1->getTypeID() == L2->getTypeID()) && "Merge:Different types");
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L1->insert(*L2It); // add the var in L2 to L1
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LiveRangeMap[*L2It] = L1; // now the elements in L2 should map
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//to L1
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}
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// set call interference for L1 from L2
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if (L2->isCallInterference())
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L1->setCallInterference();
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// add the spill costs
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L1->addSpillCost(L2->getSpillCost());
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// If L2 has a color, give L1 that color. Note that L1 may have had the same
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// color or none, but would not have a different color as asserted above.
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if (L2->hasColor())
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L1->setColor(L2->getColor());
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// Similarly, if LROfUse(L2) has a suggested color, the new range
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// must have the same color.
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if (L2->hasSuggestedColor())
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L1->setSuggestedColor(L2->getSuggestedColor());
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delete L2; // delete L2 as it is no longer needed
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}
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//---------------------------------------------------------------------------
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// Method for creating a single live range for a definition.
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// The definition must be represented by a virtual register (a Value).
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// Note: this function does *not* check that no live range exists for def.
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//---------------------------------------------------------------------------
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LiveRange*
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LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
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{
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LiveRange* DefRange = new LiveRange(); // Create a new live range,
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DefRange->insert(Def); // add Def to it,
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LiveRangeMap[Def] = DefRange; // and update the map.
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// set the register class of the new live range
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DefRange->setRegClass(RegClassList[MRI.getRegClassIDOfType(Def->getType(),
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isCC)]);
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if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
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cerr << " Creating a LR for def ";
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if (isCC) cerr << " (CC Register!)";
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cerr << " : " << RAV(Def) << "\n";
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}
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return DefRange;
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}
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LiveRange*
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LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
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{
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LiveRange *DefRange = LiveRangeMap[Def];
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// check if the LR is already there (because of multiple defs)
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if (!DefRange) {
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DefRange = createNewLiveRange(Def, isCC);
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} else { // live range already exists
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DefRange->insert(Def); // add the operand to the range
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LiveRangeMap[Def] = DefRange; // make operand point to merged set
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " Added to existing LR for def: " << RAV(Def) << "\n";
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}
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return DefRange;
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}
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//---------------------------------------------------------------------------
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// Method for constructing all live ranges in a function. It creates live
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// ranges for all values defined in the instruction stream. Also, it
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// creates live ranges for all incoming arguments of the function.
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//---------------------------------------------------------------------------
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void LiveRangeInfo::constructLiveRanges() {
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << "Constructing Live Ranges ...\n";
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// first find the live ranges for all incoming args of the function since
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// those LRs start from the start of the function
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for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
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createNewLiveRange(AI, /*isCC*/ false);
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// Now suggest hardware registers for these function args
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MRI.suggestRegs4MethodArgs(Meth, *this);
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// Now create LRs for machine instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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//
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// Also, find CALL and RETURN instructions, which need extra work.
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//
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MachineFunction &MF = MachineFunction::get(Meth);
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for (MachineFunction::iterator BBI = MF.begin(); BBI != MF.end(); ++BBI) {
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MachineBasicBlock &MBB = *BBI;
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// iterate over all the machine instructions in BB
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for(MachineBasicBlock::iterator MInstIterator = MBB.begin();
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MInstIterator != MBB.end(); ++MInstIterator) {
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MachineInstr *MInst = *MInstIterator;
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// If the machine instruction is a call/return instruction, add it to
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// CallRetInstrList for processing its args, ret value, and ret addr.
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//
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if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
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TM.getInstrInfo().isCall(MInst->getOpCode()))
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CallRetInstrList.push_back(MInst);
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// iterate over explicit MI operands and create a new LR
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// for each operand that is defined by the instruction
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for (MachineInstr::val_op_iterator OpI = MInst->begin(),
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OpE = MInst->end(); OpI != OpE; ++OpI)
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if (OpI.isDefOnly() || OpI.isDefAndUse()) {
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const Value *Def = *OpI;
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bool isCC = (OpI.getMachineOperand().getType()
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== MachineOperand::MO_CCRegister);
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LiveRange* LR = createOrAddToLiveRange(Def, isCC);
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// If the operand has a pre-assigned register,
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// set it directly in the LiveRange
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if (OpI.getMachineOperand().hasAllocatedReg()) {
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unsigned getClassId;
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LR->setColor(MRI.getClassRegNum(
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OpI.getMachineOperand().getAllocatedRegNum(),
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getClassId));
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}
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}
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// iterate over implicit MI operands and create a new LR
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// for each operand that is defined by the instruction
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for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
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if (MInst->getImplicitOp(i).opIsDefOnly() ||
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MInst->getImplicitOp(i).opIsDefAndUse()) {
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const Value *Def = MInst->getImplicitRef(i);
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LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
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// If the implicit operand has a pre-assigned register,
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// set it directly in the LiveRange
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if (MInst->getImplicitOp(i).hasAllocatedReg()) {
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unsigned getClassId;
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LR->setColor(MRI.getClassRegNum(
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MInst->getImplicitOp(i).getAllocatedRegNum(),
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getClassId));
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}
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}
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} // for all machine instructions in the BB
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} // for all BBs in function
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// Now we have to suggest clors for call and return arg live ranges.
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// Also, if there are implicit defs (e.g., retun value of a call inst)
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// they must be added to the live range list
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//
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suggestRegs4CallRets();
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if( DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << "Initial Live Ranges constructed!\n";
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}
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//---------------------------------------------------------------------------
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// If some live ranges must be colored with specific hardware registers
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// (e.g., for outgoing call args), suggesting of colors for such live
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// ranges is done using target specific function. Those functions are called
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// from this function. The target specific methods must:
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// 1) suggest colors for call and return args.
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// 2) create new LRs for implicit defs in machine instructions
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//---------------------------------------------------------------------------
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void LiveRangeInfo::suggestRegs4CallRets() {
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std::vector<MachineInstr*>::iterator It = CallRetInstrList.begin();
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for( ; It != CallRetInstrList.end(); ++It) {
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MachineInstr *MInst = *It;
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MachineOpCode OpCode = MInst->getOpCode();
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if ((TM.getInstrInfo()).isReturn(OpCode))
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MRI.suggestReg4RetValue(MInst, *this);
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else if ((TM.getInstrInfo()).isCall(OpCode))
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MRI.suggestRegs4CallArgs(MInst, *this);
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else
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assert( 0 && "Non call/ret instr in CallRetInstrList" );
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}
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}
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//--------------------------------------------------------------------------
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// The following method coalesces live ranges when possible. This method
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// must be called after the interference graph has been constructed.
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/* Algorithm:
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for each BB in function
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for each machine instruction (inst)
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for each definition (def) in inst
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for each operand (op) of inst that is a use
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if the def and op are of the same register type
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if the def and op do not interfere //i.e., not simultaneously live
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if (degree(LR of def) + degree(LR of op)) <= # avail regs
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if both LRs do not have suggested colors
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merge2IGNodes(def, op) // i.e., merge 2 LRs
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*/
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//---------------------------------------------------------------------------
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// Checks if live range LR interferes with any node assigned or suggested to
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// be assigned the specified color
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//
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inline bool InterferesWithColor(const LiveRange& LR, unsigned color)
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{
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IGNode* lrNode = LR.getUserIGNode();
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for (unsigned n=0, NN = lrNode->getNumOfNeighbors(); n < NN; n++) {
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LiveRange *neighLR = lrNode->getAdjIGNode(n)->getParentLR();
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if (neighLR->hasColor() && neighLR->getColor() == color)
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return true;
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if (neighLR->hasSuggestedColor() && neighLR->getSuggestedColor() == color)
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return true;
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}
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return false;
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}
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// Cannot coalesce if any of the following is true:
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// (1) Both LRs have suggested colors (should be "different suggested colors"?)
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// (2) Both LR1 and LR2 have colors and the colors are different
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// (but if the colors are the same, it is definitely safe to coalesce)
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// (3) LR1 has color and LR2 interferes with any LR that has the same color
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// (4) LR2 has color and LR1 interferes with any LR that has the same color
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//
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inline bool InterfsPreventCoalescing(const LiveRange& LROfDef,
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const LiveRange& LROfUse)
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{
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// (4) if they have different suggested colors, cannot coalesce
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if (LROfDef.hasSuggestedColor() && LROfUse.hasSuggestedColor())
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return true;
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// if neither has a color, nothing more to do.
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if (! LROfDef.hasColor() && ! LROfUse.hasColor())
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return false;
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// (2, 3) if L1 has color...
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if (LROfDef.hasColor()) {
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if (LROfUse.hasColor())
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return (LROfUse.getColor() != LROfDef.getColor());
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return InterferesWithColor(LROfUse, LROfDef.getColor());
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}
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// (4) else only LROfUse has a color: check if that could interfere
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return InterferesWithColor(LROfDef, LROfUse.getColor());
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}
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void LiveRangeInfo::coalesceLRs()
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{
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if(DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << "\nCoalescing LRs ...\n";
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MachineFunction &MF = MachineFunction::get(Meth);
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for (MachineFunction::iterator BBI = MF.begin(); BBI != MF.end(); ++BBI) {
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MachineBasicBlock &MBB = *BBI;
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// iterate over all the machine instructions in BB
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for(MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII){
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const MachineInstr *MI = *MII;
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if( DEBUG_RA >= RA_DEBUG_LiveRanges) {
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cerr << " *Iterating over machine instr ";
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MI->dump();
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cerr << "\n";
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}
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// iterate over MI operands to find defs
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for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
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DefE = MI->end(); DefI != DefE; ++DefI) {
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if (DefI.isDefOnly() || DefI.isDefAndUse()) { // this operand is modified
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LiveRange *LROfDef = getLiveRangeForValue( *DefI );
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RegClass *RCOfDef = LROfDef->getRegClass();
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MachineInstr::const_val_op_iterator UseI = MI->begin(),
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UseE = MI->end();
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for( ; UseI != UseE; ++UseI) { // for all uses
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LiveRange *LROfUse = getLiveRangeForValue( *UseI );
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if (!LROfUse) { // if LR of use is not found
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//don't warn about labels
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if (!isa<BasicBlock>(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " !! Warning: No LR for use " << RAV(*UseI) << "\n";
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continue; // ignore and continue
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}
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if (LROfUse == LROfDef) // nothing to merge if they are same
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continue;
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if (MRI.getRegType(LROfDef) == MRI.getRegType(LROfUse)) {
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// If the two RegTypes are the same
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if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
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unsigned CombinedDegree =
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LROfDef->getUserIGNode()->getNumOfNeighbors() +
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LROfUse->getUserIGNode()->getNumOfNeighbors();
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if (CombinedDegree > RCOfDef->getNumOfAvailRegs()) {
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// get more precise estimate of combined degree
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CombinedDegree = LROfDef->getUserIGNode()->
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getCombinedDegree(LROfUse->getUserIGNode());
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}
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if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) {
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// if both LRs do not have different pre-assigned colors
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// and both LRs do not have suggested colors
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if (! InterfsPreventCoalescing(*LROfDef, *LROfUse)) {
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RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
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unionAndUpdateLRs(LROfDef, LROfUse);
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}
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} // if combined degree is less than # of regs
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} // if def and use do not interfere
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}// if reg classes are the same
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} // for all uses
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} // if def
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} // for all defs
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} // for all machine instructions
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} // for all BBs
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << "\nCoalescing Done!\n";
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}
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/*--------------------------- Debug code for printing ---------------*/
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void LiveRangeInfo::printLiveRanges() {
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LiveRangeMapType::iterator HMI = LiveRangeMap.begin(); // hash map iterator
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cerr << "\nPrinting Live Ranges from Hash Map:\n";
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for( ; HMI != LiveRangeMap.end(); ++HMI) {
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if (HMI->first && HMI->second) {
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cerr << " Value* " << RAV(HMI->first) << "\t: ";
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if (IGNode* igNode = HMI->second->getUserIGNode())
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cerr << "LR# " << igNode->getIndex();
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else
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cerr << "LR# " << "<no-IGNode>";
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cerr << "\t:Values = "; printSet(*HMI->second); cerr << "\n";
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}
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}
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}
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