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Fix that by adding a cast to the shift expander. This came up with vector shifts on sse-less X86 CPUs. <2 x i64> = shl <2 x i64> <2 x i64> -> i64,i64 = shl i64 i64; shl i64 i64 -> i32,i32,i32,i32 = shl_parts i32 i32 i64; shl_parts i32 i32 i64 Now we cast the last two i64s to the right type. Fixes the crash in PR14668. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173615 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
1.5 KiB
LLVM
68 lines
1.5 KiB
LLVM
; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s
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define i64 @test1(i32 %xx, i32 %test) nounwind {
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%conv = zext i32 %xx to i64
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%and = and i32 %test, 7
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%sh_prom = zext i32 %and to i64
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%shl = shl i64 %conv, %sh_prom
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ret i64 %shl
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; CHECK: test1:
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; CHECK: shll %cl, %eax
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; CHECK: shrl %edx
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; CHECK: xorb $31
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; CHECK: shrl %cl, %edx
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}
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define i64 @test2(i64 %xx, i32 %test) nounwind {
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%and = and i32 %test, 7
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%sh_prom = zext i32 %and to i64
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%shl = shl i64 %xx, %sh_prom
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ret i64 %shl
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; CHECK: test2:
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; CHECK: shll %cl, %esi
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; CHECK: shrl %edx
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; CHECK: xorb $31
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; CHECK: shrl %cl, %edx
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; CHECK: orl %esi, %edx
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; CHECK: shll %cl, %eax
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}
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define i64 @test3(i64 %xx, i32 %test) nounwind {
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%and = and i32 %test, 7
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%sh_prom = zext i32 %and to i64
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%shr = lshr i64 %xx, %sh_prom
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ret i64 %shr
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; CHECK: test3:
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; CHECK: shrl %cl, %esi
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; CHECK: leal (%edx,%edx), %eax
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; CHECK: xorb $31, %cl
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; CHECK: shll %cl, %eax
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; CHECK: orl %esi, %eax
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; CHECK: shrl %cl, %edx
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}
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define i64 @test4(i64 %xx, i32 %test) nounwind {
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%and = and i32 %test, 7
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%sh_prom = zext i32 %and to i64
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%shr = ashr i64 %xx, %sh_prom
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ret i64 %shr
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; CHECK: test4:
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; CHECK: shrl %cl, %esi
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; CHECK: leal (%edx,%edx), %eax
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; CHECK: xorb $31, %cl
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; CHECK: shll %cl, %eax
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; CHECK: orl %esi, %eax
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; CHECK: sarl %cl, %edx
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}
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; PR14668
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define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) {
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%shl = shl <2 x i64> %A, %B
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ret <2 x i64> %shl
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; CHECK: test5
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; CHECK: shl
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; CHECK: shldl
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; CHECK: shl
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; CHECK: shldl
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}
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