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Motivation: Improve the parsing of not usual (different from registers or immediates) operand forms. This commit implements only the generic support. The ARM specific modifications will come next. A table like the one below is autogenerated for every instruction containing a 'ParserMethod' in its AsmOperandClass static const OperandMatchEntry OperandMatchTable[20] = { /* Mnemonic, Operand List Mask, Operand Class, Features */ { "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 }, { "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM }, A matcher function very similar (but lot more naive) to MatchInstructionImpl scans the table. After the mnemonic match, the features are checked and if the "to be parsed" operand index is present in the mask, there's a real match. Then, a switch like the one below dispatch the parsing to the custom method provided in 'ParseMethod': case MCK_Coproc: return TryParseCoprocessorOperandName(Operands); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125030 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
Mangler.h | ||
SubtargetFeature.h | ||
Target.td | ||
TargetAsmBackend.h | ||
TargetAsmInfo.h | ||
TargetAsmLexer.h | ||
TargetAsmParser.h | ||
TargetCallingConv.h | ||
TargetCallingConv.td | ||
TargetData.h | ||
TargetELFWriterInfo.h | ||
TargetFrameLowering.h | ||
TargetInstrDesc.h | ||
TargetInstrInfo.h | ||
TargetInstrItineraries.h | ||
TargetIntrinsicInfo.h | ||
TargetJITInfo.h | ||
TargetLowering.h | ||
TargetLoweringObjectFile.h | ||
TargetMachine.h | ||
TargetOpcodes.h | ||
TargetOptions.h | ||
TargetRegisterInfo.h | ||
TargetRegistry.h | ||
TargetSchedule.td | ||
TargetSelect.h | ||
TargetSelectionDAG.td | ||
TargetSelectionDAGInfo.h | ||
TargetSubtarget.h |