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The value mapping gets confused about which original values have multiple new definitions so they may need phi insertions. This could probably be simplified by letting enterIntvBefore() take a live range to be added following the instruction. As long as the range stays inside the same basic block, value mapping shouldn't be a problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123926 91177308-0d34-0410-b5e6-96231b3b80d8
1032 lines
36 KiB
C++
1032 lines
36 KiB
C++
//===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RAGreedy function pass for register allocation in
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// optimized builds.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "AllocationOrder.h"
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#include "LiveIntervalUnion.h"
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#include "LiveRangeEdit.h"
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#include "RegAllocBase.h"
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#include "Spiller.h"
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#include "SpillPlacement.h"
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#include "SplitKit.h"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Function.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/EdgeBundles.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineLoopRanges.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Timer.h"
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using namespace llvm;
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static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
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createGreedyRegisterAllocator);
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namespace {
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class RAGreedy : public MachineFunctionPass, public RegAllocBase {
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// context
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MachineFunction *MF;
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BitVector ReservedRegs;
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// analyses
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SlotIndexes *Indexes;
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LiveStacks *LS;
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MachineDominatorTree *DomTree;
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MachineLoopInfo *Loops;
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MachineLoopRanges *LoopRanges;
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EdgeBundles *Bundles;
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SpillPlacement *SpillPlacer;
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// state
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std::auto_ptr<Spiller> SpillerInstance;
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std::auto_ptr<SplitAnalysis> SA;
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// splitting state.
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/// All basic blocks where the current register is live.
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SmallVector<SpillPlacement::BlockConstraint, 8> SpillConstraints;
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/// Additional information about basic blocks where the current variable is
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/// live. Such a block will look like one of these templates:
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///
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/// 1. | o---x | Internal to block. Variable is only live in this block.
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/// 2. |---x | Live-in, kill.
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/// 3. | o---| Def, live-out.
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/// 4. |---x o---| Live-in, kill, def, live-out.
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/// 5. |---o---o---| Live-through with uses or defs.
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/// 6. |-----------| Live-through without uses. Transparent.
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///
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struct BlockInfo {
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MachineBasicBlock *MBB;
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SlotIndex FirstUse; ///< First instr using current reg.
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SlotIndex LastUse; ///< Last instr using current reg.
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SlotIndex Kill; ///< Interval end point inside block.
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SlotIndex Def; ///< Interval start point inside block.
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bool Uses; ///< Current reg has uses or defs in block.
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bool LiveThrough; ///< Live in whole block (Templ 5. or 6. above).
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bool LiveIn; ///< Current reg is live in.
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bool LiveOut; ///< Current reg is live out.
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// Per-interference pattern scratch data.
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bool OverlapEntry; ///< Interference overlaps entering interval.
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bool OverlapExit; ///< Interference overlaps exiting interval.
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};
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/// Basic blocks where var is live. This array is parallel to
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/// SpillConstraints.
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SmallVector<BlockInfo, 8> LiveBlocks;
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public:
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RAGreedy();
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/// Return the pass name.
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virtual const char* getPassName() const {
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return "Greedy Register Allocator";
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}
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/// RAGreedy analysis usage.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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virtual Spiller &spiller() { return *SpillerInstance; }
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virtual float getPriority(LiveInterval *LI);
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virtual unsigned selectOrSplit(LiveInterval&,
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SmallVectorImpl<LiveInterval*>&);
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/// Perform register allocation.
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virtual bool runOnMachineFunction(MachineFunction &mf);
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static char ID;
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private:
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bool checkUncachedInterference(LiveInterval&, unsigned);
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LiveInterval *getSingleInterference(LiveInterval&, unsigned);
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bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
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bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
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float calcInterferenceWeight(LiveInterval&, unsigned);
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void calcLiveBlockInfo(LiveInterval&);
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float calcInterferenceInfo(LiveInterval&, unsigned);
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float calcGlobalSplitCost(const BitVector&);
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void splitAroundRegion(LiveInterval&, unsigned, const BitVector&,
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SmallVectorImpl<LiveInterval*>&);
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unsigned tryReassign(LiveInterval&, AllocationOrder&);
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unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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unsigned trySplit(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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unsigned trySpillInterferences(LiveInterval&, AllocationOrder&,
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SmallVectorImpl<LiveInterval*>&);
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};
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} // end anonymous namespace
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char RAGreedy::ID = 0;
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FunctionPass* llvm::createGreedyRegisterAllocator() {
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return new RAGreedy();
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}
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RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
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initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
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initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
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initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
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initializeMachineLoopRangesPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
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initializeSpillPlacementPass(*PassRegistry::getPassRegistry());
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}
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void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<AliasAnalysis>();
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AU.addRequired<LiveIntervals>();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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if (StrongPHIElim)
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AU.addRequiredID(StrongPHIEliminationID);
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AU.addRequiredTransitive<RegisterCoalescer>();
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AU.addRequired<CalculateSpillWeights>();
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<MachineLoopRanges>();
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AU.addPreserved<MachineLoopRanges>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<VirtRegMap>();
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AU.addRequired<EdgeBundles>();
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AU.addRequired<SpillPlacement>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void RAGreedy::releaseMemory() {
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SpillerInstance.reset(0);
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RegAllocBase::releaseMemory();
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}
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float RAGreedy::getPriority(LiveInterval *LI) {
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float Priority = LI->weight;
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// Prioritize hinted registers so they are allocated first.
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std::pair<unsigned, unsigned> Hint;
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if (Hint.first || Hint.second) {
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// The hint can be target specific, a virtual register, or a physreg.
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Priority *= 2;
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// Prefer physreg hints above anything else.
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if (Hint.first == 0 && TargetRegisterInfo::isPhysicalRegister(Hint.second))
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Priority *= 2;
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}
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return Priority;
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}
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//===----------------------------------------------------------------------===//
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// Register Reassignment
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//===----------------------------------------------------------------------===//
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// Check interference without using the cache.
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bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
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unsigned PhysReg) {
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for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
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LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
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if (subQ.checkInterference())
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return true;
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}
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return false;
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}
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/// getSingleInterference - Return the single interfering virtual register
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/// assigned to PhysReg. Return 0 if more than one virtual register is
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/// interfering.
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LiveInterval *RAGreedy::getSingleInterference(LiveInterval &VirtReg,
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unsigned PhysReg) {
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// Check physreg and aliases.
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LiveInterval *Interference = 0;
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for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) {
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LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI);
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if (Q.checkInterference()) {
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if (Interference)
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return 0;
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Q.collectInterferingVRegs(1);
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if (!Q.seenAllInterferences())
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return 0;
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Interference = Q.interferingVRegs().front();
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}
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}
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return Interference;
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}
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// Attempt to reassign this virtual register to a different physical register.
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//
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// FIXME: we are not yet caching these "second-level" interferences discovered
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// in the sub-queries. These interferences can change with each call to
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// selectOrSplit. However, we could implement a "may-interfere" cache that
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// could be conservatively dirtied when we reassign or split.
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//
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// FIXME: This may result in a lot of alias queries. We could summarize alias
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// live intervals in their parent register's live union, but it's messy.
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bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
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unsigned WantedPhysReg) {
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assert(TargetRegisterInfo::isVirtualRegister(InterferingVReg.reg) &&
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"Can only reassign virtual registers");
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assert(TRI->regsOverlap(WantedPhysReg, VRM->getPhys(InterferingVReg.reg)) &&
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"inconsistent phys reg assigment");
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AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs);
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while (unsigned PhysReg = Order.next()) {
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// Don't reassign to a WantedPhysReg alias.
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if (TRI->regsOverlap(PhysReg, WantedPhysReg))
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continue;
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if (checkUncachedInterference(InterferingVReg, PhysReg))
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continue;
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// Reassign the interfering virtual reg to this physical reg.
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unsigned OldAssign = VRM->getPhys(InterferingVReg.reg);
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DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
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TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n');
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PhysReg2LiveUnion[OldAssign].extract(InterferingVReg);
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VRM->clearVirt(InterferingVReg.reg);
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VRM->assignVirt2Phys(InterferingVReg.reg, PhysReg);
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PhysReg2LiveUnion[PhysReg].unify(InterferingVReg);
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return true;
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}
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return false;
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}
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/// reassignInterferences - Reassign all interferences to different physical
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/// registers such that Virtreg can be assigned to PhysReg.
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/// Currently this only works with a single interference.
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/// @param VirtReg Currently unassigned virtual register.
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/// @param PhysReg Physical register to be cleared.
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/// @return True on success, false if nothing was changed.
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bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) {
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LiveInterval *InterferingVReg = getSingleInterference(VirtReg, PhysReg);
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if (!InterferingVReg)
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return false;
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if (TargetRegisterInfo::isPhysicalRegister(InterferingVReg->reg))
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return false;
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return reassignVReg(*InterferingVReg, PhysReg);
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}
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/// tryReassign - Try to reassign interferences to different physregs.
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/// @param VirtReg Currently unassigned virtual register.
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/// @param Order Physregs to try.
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/// @return Physreg to assign VirtReg, or 0.
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unsigned RAGreedy::tryReassign(LiveInterval &VirtReg, AllocationOrder &Order) {
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NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
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Order.rewind();
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while (unsigned PhysReg = Order.next())
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if (reassignInterferences(VirtReg, PhysReg))
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return PhysReg;
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return 0;
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}
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//===----------------------------------------------------------------------===//
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// Region Splitting
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//===----------------------------------------------------------------------===//
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/// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
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/// where VirtReg is live.
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/// The SpillConstraints array is minimally initialized with MBB->getNumber().
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void RAGreedy::calcLiveBlockInfo(LiveInterval &VirtReg) {
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LiveBlocks.clear();
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SpillConstraints.clear();
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assert(!VirtReg.empty() && "Cannot allocate an empty interval");
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LiveInterval::const_iterator LVI = VirtReg.begin();
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LiveInterval::const_iterator LVE = VirtReg.end();
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SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
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UseI = SA->UseSlots.begin();
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UseE = SA->UseSlots.end();
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// Loop over basic blocks where VirtReg is live.
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MachineFunction::iterator MFI = Indexes->getMBBFromIndex(LVI->start);
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for (;;) {
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// Block constraints depend on the interference pattern.
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// Just allocate them here, don't compute anything.
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SpillPlacement::BlockConstraint BC;
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BC.Number = MFI->getNumber();
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SpillConstraints.push_back(BC);
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BlockInfo BI;
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BI.MBB = MFI;
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SlotIndex Start, Stop;
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tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
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// LVI is the first live segment overlapping MBB.
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BI.LiveIn = LVI->start <= Start;
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if (!BI.LiveIn)
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BI.Def = LVI->start;
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// Find the first and last uses in the block.
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BI.Uses = SA->hasUses(MFI);
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if (BI.Uses && UseI != UseE) {
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BI.FirstUse = *UseI;
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assert(BI.FirstUse >= Start);
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do ++UseI;
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while (UseI != UseE && *UseI < Stop);
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BI.LastUse = UseI[-1];
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assert(BI.LastUse < Stop);
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}
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// Look for gaps in the live range.
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bool hasGap = false;
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BI.LiveOut = true;
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while (LVI->end < Stop) {
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SlotIndex LastStop = LVI->end;
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if (++LVI == LVE || LVI->start >= Stop) {
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BI.Kill = LastStop;
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BI.LiveOut = false;
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break;
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}
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if (LastStop < LVI->start) {
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hasGap = true;
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BI.Kill = LastStop;
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BI.Def = LVI->start;
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}
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}
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// Don't set LiveThrough when the block has a gap.
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BI.LiveThrough = !hasGap && BI.LiveIn && BI.LiveOut;
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LiveBlocks.push_back(BI);
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// LVI is now at LVE or LVI->end >= Stop.
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if (LVI == LVE)
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break;
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// Live segment ends exactly at Stop. Move to the next segment.
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if (LVI->end == Stop && ++LVI == LVE)
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break;
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// Pick the next basic block.
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if (LVI->start < Stop)
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++MFI;
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else
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MFI = Indexes->getMBBFromIndex(LVI->start);
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}
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}
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/// calcInterferenceInfo - Compute per-block outgoing and ingoing constraints
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/// when considering interference from PhysReg. Also compute an optimistic local
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/// cost of this interference pattern.
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///
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/// The final cost of a split is the local cost + global cost of preferences
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/// broken by SpillPlacement.
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///
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float RAGreedy::calcInterferenceInfo(LiveInterval &VirtReg, unsigned PhysReg) {
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// Reset interference dependent info.
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for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
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BlockInfo &BI = LiveBlocks[i];
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SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
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BC.Entry = (BI.Uses && BI.LiveIn) ?
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SpillPlacement::PrefReg : SpillPlacement::DontCare;
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BC.Exit = (BI.Uses && BI.LiveOut) ?
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SpillPlacement::PrefReg : SpillPlacement::DontCare;
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BI.OverlapEntry = BI.OverlapExit = false;
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}
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// Add interference info from each PhysReg alias.
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for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
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if (!query(VirtReg, *AI).checkInterference())
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continue;
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DEBUG(PhysReg2LiveUnion[*AI].print(dbgs(), TRI));
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LiveIntervalUnion::SegmentIter IntI =
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PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
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if (!IntI.valid())
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continue;
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for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
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BlockInfo &BI = LiveBlocks[i];
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SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
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SlotIndex Start, Stop;
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tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
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// Skip interference-free blocks.
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if (IntI.start() >= Stop)
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continue;
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// Handle transparent blocks with interference separately.
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// Transparent blocks never incur any fixed cost.
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if (BI.LiveThrough && !BI.Uses) {
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// Check if interference is live-in - force spill.
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if (BC.Entry != SpillPlacement::MustSpill) {
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BC.Entry = SpillPlacement::PrefSpill;
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IntI.advanceTo(Start);
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if (IntI.valid() && IntI.start() <= Start)
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BC.Entry = SpillPlacement::MustSpill;
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}
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// Check if interference is live-out - force spill.
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if (BC.Exit != SpillPlacement::MustSpill) {
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BC.Exit = SpillPlacement::PrefSpill;
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IntI.advanceTo(Stop);
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if (IntI.valid() && IntI.start() < Stop)
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BC.Exit = SpillPlacement::MustSpill;
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}
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// Nothing more to do for this transparent block.
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if (!IntI.valid())
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break;
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continue;
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}
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// Now we only have blocks with uses left.
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// Check if the interference overlaps the uses.
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assert(BI.Uses && "Non-transparent block without any uses");
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// Check interference on entry.
|
|
if (BI.LiveIn && BC.Entry != SpillPlacement::MustSpill) {
|
|
IntI.advanceTo(Start);
|
|
if (!IntI.valid())
|
|
break;
|
|
|
|
// Interference is live-in - force spill.
|
|
if (IntI.start() <= Start)
|
|
BC.Entry = SpillPlacement::MustSpill;
|
|
// Not live in, but before the first use.
|
|
else if (IntI.start() < BI.FirstUse)
|
|
BC.Entry = SpillPlacement::PrefSpill;
|
|
}
|
|
|
|
// Does interference overlap the uses in the entry segment
|
|
// [FirstUse;Kill)?
|
|
if (BI.LiveIn && !BI.OverlapEntry) {
|
|
IntI.advanceTo(BI.FirstUse);
|
|
if (!IntI.valid())
|
|
break;
|
|
// A live-through interval has no kill.
|
|
// Check [FirstUse;LastUse) instead.
|
|
if (IntI.start() < (BI.LiveThrough ? BI.LastUse : BI.Kill))
|
|
BI.OverlapEntry = true;
|
|
}
|
|
|
|
// Does interference overlap the uses in the exit segment [Def;LastUse)?
|
|
if (BI.LiveOut && !BI.LiveThrough && !BI.OverlapExit) {
|
|
IntI.advanceTo(BI.Def);
|
|
if (!IntI.valid())
|
|
break;
|
|
if (IntI.start() < BI.LastUse)
|
|
BI.OverlapExit = true;
|
|
}
|
|
|
|
// Check interference on exit.
|
|
if (BI.LiveOut && BC.Exit != SpillPlacement::MustSpill) {
|
|
// Check interference between LastUse and Stop.
|
|
if (BC.Exit != SpillPlacement::PrefSpill) {
|
|
IntI.advanceTo(BI.LastUse);
|
|
if (!IntI.valid())
|
|
break;
|
|
if (IntI.start() < Stop)
|
|
BC.Exit = SpillPlacement::PrefSpill;
|
|
}
|
|
// Is the interference live-out?
|
|
IntI.advanceTo(Stop);
|
|
if (!IntI.valid())
|
|
break;
|
|
if (IntI.start() < Stop)
|
|
BC.Exit = SpillPlacement::MustSpill;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Accumulate a local cost of this interference pattern.
|
|
float LocalCost = 0;
|
|
for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
|
|
BlockInfo &BI = LiveBlocks[i];
|
|
if (!BI.Uses)
|
|
continue;
|
|
SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
|
|
unsigned Inserts = 0;
|
|
|
|
// Do we need spill code for the entry segment?
|
|
if (BI.LiveIn)
|
|
Inserts += BI.OverlapEntry || BC.Entry != SpillPlacement::PrefReg;
|
|
|
|
// For the exit segment?
|
|
if (BI.LiveOut)
|
|
Inserts += BI.OverlapExit || BC.Exit != SpillPlacement::PrefReg;
|
|
|
|
// The local cost of spill code in this block is the block frequency times
|
|
// the number of spill instructions inserted.
|
|
if (Inserts)
|
|
LocalCost += Inserts * SpillPlacer->getBlockFrequency(BI.MBB);
|
|
}
|
|
DEBUG(dbgs() << "Local cost of " << PrintReg(PhysReg, TRI) << " = "
|
|
<< LocalCost << '\n');
|
|
return LocalCost;
|
|
}
|
|
|
|
/// calcGlobalSplitCost - Return the global split cost of following the split
|
|
/// pattern in LiveBundles. This cost should be added to the local cost of the
|
|
/// interference pattern in SpillConstraints.
|
|
///
|
|
float RAGreedy::calcGlobalSplitCost(const BitVector &LiveBundles) {
|
|
float GlobalCost = 0;
|
|
for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
|
|
SpillPlacement::BlockConstraint &BC = SpillConstraints[i];
|
|
unsigned Inserts = 0;
|
|
// Broken entry preference?
|
|
Inserts += LiveBundles[Bundles->getBundle(BC.Number, 0)] !=
|
|
(BC.Entry == SpillPlacement::PrefReg);
|
|
// Broken exit preference?
|
|
Inserts += LiveBundles[Bundles->getBundle(BC.Number, 1)] !=
|
|
(BC.Exit == SpillPlacement::PrefReg);
|
|
if (Inserts)
|
|
GlobalCost += Inserts * SpillPlacer->getBlockFrequency(LiveBlocks[i].MBB);
|
|
}
|
|
DEBUG(dbgs() << "Global cost = " << GlobalCost << '\n');
|
|
return GlobalCost;
|
|
}
|
|
|
|
/// splitAroundRegion - Split VirtReg around the region determined by
|
|
/// LiveBundles. Make an effort to avoid interference from PhysReg.
|
|
///
|
|
/// The 'register' interval is going to contain as many uses as possible while
|
|
/// avoiding interference. The 'stack' interval is the complement constructed by
|
|
/// SplitEditor. It will contain the rest.
|
|
///
|
|
void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
|
|
const BitVector &LiveBundles,
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
|
DEBUG({
|
|
dbgs() << "Splitting around region for " << PrintReg(PhysReg, TRI)
|
|
<< " with bundles";
|
|
for (int i = LiveBundles.find_first(); i>=0; i = LiveBundles.find_next(i))
|
|
dbgs() << " EB#" << i;
|
|
dbgs() << ".\n";
|
|
});
|
|
|
|
// First compute interference ranges in the live blocks.
|
|
typedef std::pair<SlotIndex, SlotIndex> IndexPair;
|
|
SmallVector<IndexPair, 8> InterferenceRanges;
|
|
InterferenceRanges.resize(LiveBlocks.size());
|
|
for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
|
|
if (!query(VirtReg, *AI).checkInterference())
|
|
continue;
|
|
LiveIntervalUnion::SegmentIter IntI =
|
|
PhysReg2LiveUnion[*AI].find(VirtReg.beginIndex());
|
|
if (!IntI.valid())
|
|
continue;
|
|
for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
|
|
BlockInfo &BI = LiveBlocks[i];
|
|
if (!BI.Uses)
|
|
continue;
|
|
IndexPair &IP = InterferenceRanges[i];
|
|
SlotIndex Start, Stop;
|
|
tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
|
|
// Skip interference-free blocks.
|
|
if (IntI.start() >= Stop)
|
|
continue;
|
|
|
|
// First interference in block.
|
|
if (BI.LiveIn) {
|
|
IntI.advanceTo(Start);
|
|
if (!IntI.valid())
|
|
break;
|
|
if (!IP.first.isValid() || IntI.start() < IP.first)
|
|
IP.first = IntI.start();
|
|
}
|
|
|
|
// Last interference in block.
|
|
if (BI.LiveOut) {
|
|
IntI.advanceTo(Stop);
|
|
if (!IntI.valid() || IntI.start() >= Stop)
|
|
--IntI;
|
|
if (!IP.second.isValid() || IntI.stop() > IP.second)
|
|
IP.second = IntI.stop();
|
|
}
|
|
}
|
|
}
|
|
|
|
SmallVector<LiveInterval*, 4> SpillRegs;
|
|
LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
|
|
SplitEditor SE(*SA, *LIS, *VRM, *DomTree, LREdit);
|
|
|
|
// Ranges to add to the register interval after all defs are in place.
|
|
SmallVector<IndexPair, 8> UseRanges;
|
|
|
|
// Create the main cross-block interval.
|
|
SE.openIntv();
|
|
|
|
// First add all defs that are live out of a block.
|
|
for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
|
|
BlockInfo &BI = LiveBlocks[i];
|
|
bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
|
|
bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
|
|
|
|
// Should the register be live out?
|
|
if (!BI.LiveOut || !RegOut)
|
|
continue;
|
|
|
|
IndexPair &IP = InterferenceRanges[i];
|
|
SlotIndex Start, Stop;
|
|
tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
|
|
|
|
DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
|
|
<< Bundles->getBundle(BI.MBB->getNumber(), 1));
|
|
|
|
// Check interference leaving the block.
|
|
if (!IP.second.isValid() || IP.second < Start) {
|
|
// Block is interference-free.
|
|
DEBUG(dbgs() << ", no interference");
|
|
if (!BI.Uses) {
|
|
assert(BI.LiveThrough && "No uses, but not live through block?");
|
|
// Block is live-through without interference.
|
|
DEBUG(dbgs() << ", no uses"
|
|
<< (RegIn ? ", live-through.\n" : ", stack in.\n"));
|
|
if (!RegIn)
|
|
SE.enterIntvAtEnd(*BI.MBB);
|
|
continue;
|
|
}
|
|
if (!BI.LiveThrough) {
|
|
DEBUG(dbgs() << ", not live-through.\n");
|
|
SE.enterIntvBefore(BI.Def);
|
|
UseRanges.push_back(IndexPair(BI.Def, Stop));
|
|
continue;
|
|
}
|
|
if (!RegIn) {
|
|
// Block is live-through, but entry bundle is on the stack.
|
|
// Reload just before the first use.
|
|
DEBUG(dbgs() << ", not live-in, enter before first use.\n");
|
|
SE.enterIntvBefore(BI.FirstUse);
|
|
UseRanges.push_back(IndexPair(BI.FirstUse, Stop));
|
|
continue;
|
|
}
|
|
DEBUG(dbgs() << ", live-through.\n");
|
|
continue;
|
|
}
|
|
|
|
// Block has interference.
|
|
DEBUG(dbgs() << ", interference to " << IP.second);
|
|
if (!BI.Uses) {
|
|
// No uses in block, avoid interference by reloading as late as possible.
|
|
DEBUG(dbgs() << ", no uses.\n");
|
|
SE.enterIntvAtEnd(*BI.MBB);
|
|
continue;
|
|
}
|
|
if (IP.second < BI.LastUse) {
|
|
// There are interference-free uses at the end of the block.
|
|
// Find the first use that can get the live-out register.
|
|
SmallVectorImpl<SlotIndex>::const_iterator UI =
|
|
std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), IP.second);
|
|
assert(UI != SA->UseSlots.end() && "Couldn't find last use");
|
|
SlotIndex Use = *UI;
|
|
DEBUG(dbgs() << ", free use at " << Use << ".\n");
|
|
assert(Use <= BI.LastUse && "Couldn't find last use");
|
|
SE.enterIntvBefore(Use);
|
|
UseRanges.push_back(IndexPair(Use, Stop));
|
|
continue;
|
|
}
|
|
|
|
// Interference is after the last use.
|
|
DEBUG(dbgs() << " after last use.\n");
|
|
SE.enterIntvAtEnd(*BI.MBB);
|
|
}
|
|
|
|
// Add the live-out ranges following the defs.
|
|
// We must wait until all defs have been inserted, otherwise SplitKit gets
|
|
// confused about the value mapping.
|
|
for (unsigned i = 0, e = UseRanges.size(); i != e; ++i)
|
|
SE.useIntv(UseRanges[i].first, UseRanges[i].second);
|
|
|
|
// Now all defs leading to live bundles are handled, do everything else.
|
|
for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
|
|
BlockInfo &BI = LiveBlocks[i];
|
|
bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)];
|
|
bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)];
|
|
|
|
// Is the register live-in?
|
|
if (!BI.LiveIn || !RegIn)
|
|
continue;
|
|
|
|
// We have an incoming register. Check for interference.
|
|
IndexPair &IP = InterferenceRanges[i];
|
|
SlotIndex Start, Stop;
|
|
tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
|
|
|
|
DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
|
|
<< " -> BB#" << BI.MBB->getNumber());
|
|
|
|
// Check interference entering the block.
|
|
if (!IP.first.isValid() || IP.first > Stop) {
|
|
// Block is interference-free.
|
|
DEBUG(dbgs() << ", no interference");
|
|
if (!BI.Uses) {
|
|
assert(BI.LiveThrough && "No uses, but not live through block?");
|
|
// Block is live-through without interference.
|
|
if (RegOut) {
|
|
DEBUG(dbgs() << ", no uses, live-through.\n");
|
|
SE.useIntv(Start, Stop);
|
|
} else {
|
|
DEBUG(dbgs() << ", no uses, stack-out.\n");
|
|
SE.leaveIntvAtTop(*BI.MBB);
|
|
}
|
|
continue;
|
|
}
|
|
if (!BI.LiveThrough) {
|
|
DEBUG(dbgs() << ", killed in block.\n");
|
|
SE.useIntv(Start, BI.Kill.getBoundaryIndex());
|
|
SE.leaveIntvAfter(BI.Kill);
|
|
continue;
|
|
}
|
|
if (!RegOut) {
|
|
// Block is live-through, but exit bundle is on the stack.
|
|
// Spill immediately after the last use.
|
|
DEBUG(dbgs() << ", uses, stack-out.\n");
|
|
SE.useIntv(Start, BI.LastUse.getBoundaryIndex());
|
|
SE.leaveIntvAfter(BI.LastUse);
|
|
continue;
|
|
}
|
|
// Register is live-through.
|
|
DEBUG(dbgs() << ", uses, live-through.\n");
|
|
SE.useIntv(Start, Stop);
|
|
continue;
|
|
}
|
|
|
|
// Block has interference.
|
|
DEBUG(dbgs() << ", interference from " << IP.first);
|
|
if (!BI.Uses) {
|
|
// No uses in block, avoid interference by spilling as soon as possible.
|
|
DEBUG(dbgs() << ", no uses.\n");
|
|
SE.leaveIntvAtTop(*BI.MBB);
|
|
continue;
|
|
}
|
|
if (IP.first > BI.FirstUse) {
|
|
// There are interference-free uses at the beginning of the block.
|
|
// Find the last use that can get the register.
|
|
SmallVectorImpl<SlotIndex>::const_iterator UI =
|
|
std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), IP.first);
|
|
assert(UI != SA->UseSlots.begin() && "Couldn't find first use");
|
|
SlotIndex Use = (--UI)->getBoundaryIndex();
|
|
DEBUG(dbgs() << ", free use at " << *UI << ".\n");
|
|
assert(Use >= BI.FirstUse && Use < IP.first);
|
|
SE.useIntv(Start, Use);
|
|
SE.leaveIntvAfter(Use);
|
|
continue;
|
|
}
|
|
|
|
// Interference is before the first use.
|
|
DEBUG(dbgs() << " before first use.\n");
|
|
SE.leaveIntvAtTop(*BI.MBB);
|
|
}
|
|
|
|
SE.closeIntv();
|
|
|
|
// FIXME: Should we be more aggressive about splitting the stack region into
|
|
// per-block segments? The current approach allows the stack region to
|
|
// separate into connected components. Some components may be allocatable.
|
|
SE.finish();
|
|
|
|
if (VerifyEnabled)
|
|
MF->verify(this, "After splitting live range around region");
|
|
}
|
|
|
|
unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
|
calcLiveBlockInfo(VirtReg);
|
|
BitVector LiveBundles, BestBundles;
|
|
float BestCost = 0;
|
|
unsigned BestReg = 0;
|
|
Order.rewind();
|
|
while (unsigned PhysReg = Order.next()) {
|
|
float Cost = calcInterferenceInfo(VirtReg, PhysReg);
|
|
if (BestReg && Cost >= BestCost)
|
|
continue;
|
|
|
|
SpillPlacer->placeSpills(SpillConstraints, LiveBundles);
|
|
// No live bundles, defer to splitSingleBlocks().
|
|
if (!LiveBundles.any())
|
|
continue;
|
|
|
|
Cost += calcGlobalSplitCost(LiveBundles);
|
|
if (!BestReg || Cost < BestCost) {
|
|
BestReg = PhysReg;
|
|
BestCost = Cost;
|
|
BestBundles.swap(LiveBundles);
|
|
}
|
|
}
|
|
|
|
if (!BestReg)
|
|
return 0;
|
|
|
|
splitAroundRegion(VirtReg, BestReg, BestBundles, NewVRegs);
|
|
return 0;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Live Range Splitting
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// trySplit - Try to split VirtReg or one of its interferences, making it
|
|
/// assignable.
|
|
/// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
|
|
unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
|
|
SmallVectorImpl<LiveInterval*>&NewVRegs) {
|
|
NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
|
|
SA->analyze(&VirtReg);
|
|
|
|
// Don't attempt splitting on local intervals for now. TBD.
|
|
if (LIS->intervalIsInOneMBB(VirtReg))
|
|
return 0;
|
|
|
|
// First try to split around a region spanning multiple blocks.
|
|
unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
|
|
if (PhysReg || !NewVRegs.empty())
|
|
return PhysReg;
|
|
|
|
// Then isolate blocks with multiple uses.
|
|
SplitAnalysis::BlockPtrSet Blocks;
|
|
if (SA->getMultiUseBlocks(Blocks)) {
|
|
SmallVector<LiveInterval*, 4> SpillRegs;
|
|
LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
|
|
SplitEditor(*SA, *LIS, *VRM, *DomTree, LREdit).splitSingleBlocks(Blocks);
|
|
}
|
|
|
|
// Don't assign any physregs.
|
|
return 0;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Spilling
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// calcInterferenceWeight - Calculate the combined spill weight of
|
|
/// interferences when assigning VirtReg to PhysReg.
|
|
float RAGreedy::calcInterferenceWeight(LiveInterval &VirtReg, unsigned PhysReg){
|
|
float Sum = 0;
|
|
for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) {
|
|
LiveIntervalUnion::Query &Q = query(VirtReg, *AI);
|
|
Q.collectInterferingVRegs();
|
|
if (Q.seenUnspillableVReg())
|
|
return HUGE_VALF;
|
|
for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i)
|
|
Sum += Q.interferingVRegs()[i]->weight;
|
|
}
|
|
return Sum;
|
|
}
|
|
|
|
/// trySpillInterferences - Try to spill interfering registers instead of the
|
|
/// current one. Only do it if the accumulated spill weight is smaller than the
|
|
/// current spill weight.
|
|
unsigned RAGreedy::trySpillInterferences(LiveInterval &VirtReg,
|
|
AllocationOrder &Order,
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
|
NamedRegionTimer T("Spill Interference", TimerGroupName, TimePassesIsEnabled);
|
|
unsigned BestPhys = 0;
|
|
float BestWeight = 0;
|
|
|
|
Order.rewind();
|
|
while (unsigned PhysReg = Order.next()) {
|
|
float Weight = calcInterferenceWeight(VirtReg, PhysReg);
|
|
if (Weight == HUGE_VALF || Weight >= VirtReg.weight)
|
|
continue;
|
|
if (!BestPhys || Weight < BestWeight)
|
|
BestPhys = PhysReg, BestWeight = Weight;
|
|
}
|
|
|
|
// No candidates found.
|
|
if (!BestPhys)
|
|
return 0;
|
|
|
|
// Collect all interfering registers.
|
|
SmallVector<LiveInterval*, 8> Spills;
|
|
for (const unsigned *AI = TRI->getOverlaps(BestPhys); *AI; ++AI) {
|
|
LiveIntervalUnion::Query &Q = query(VirtReg, *AI);
|
|
Spills.append(Q.interferingVRegs().begin(), Q.interferingVRegs().end());
|
|
for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) {
|
|
LiveInterval *VReg = Q.interferingVRegs()[i];
|
|
PhysReg2LiveUnion[*AI].extract(*VReg);
|
|
VRM->clearVirt(VReg->reg);
|
|
}
|
|
}
|
|
|
|
// Spill them all.
|
|
DEBUG(dbgs() << "spilling " << Spills.size() << " interferences with weight "
|
|
<< BestWeight << '\n');
|
|
for (unsigned i = 0, e = Spills.size(); i != e; ++i)
|
|
spiller().spill(Spills[i], NewVRegs, Spills);
|
|
return BestPhys;
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Main Entry Point
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
|
|
SmallVectorImpl<LiveInterval*> &NewVRegs) {
|
|
// First try assigning a free register.
|
|
AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
|
|
while (unsigned PhysReg = Order.next()) {
|
|
if (!checkPhysRegInterference(VirtReg, PhysReg))
|
|
return PhysReg;
|
|
}
|
|
|
|
// Try to reassign interferences.
|
|
if (unsigned PhysReg = tryReassign(VirtReg, Order))
|
|
return PhysReg;
|
|
|
|
assert(NewVRegs.empty() && "Cannot append to existing NewVRegs");
|
|
|
|
// Try splitting VirtReg or interferences.
|
|
unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
|
|
if (PhysReg || !NewVRegs.empty())
|
|
return PhysReg;
|
|
|
|
// Try to spill another interfering reg with less spill weight.
|
|
PhysReg = trySpillInterferences(VirtReg, Order, NewVRegs);
|
|
if (PhysReg)
|
|
return PhysReg;
|
|
|
|
// Finally spill VirtReg itself.
|
|
NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
|
|
SmallVector<LiveInterval*, 1> pendingSpills;
|
|
spiller().spill(&VirtReg, NewVRegs, pendingSpills);
|
|
|
|
// The live virtual register requesting allocation was spilled, so tell
|
|
// the caller not to allocate anything during this round.
|
|
return 0;
|
|
}
|
|
|
|
bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
|
|
DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
|
|
<< "********** Function: "
|
|
<< ((Value*)mf.getFunction())->getName() << '\n');
|
|
|
|
MF = &mf;
|
|
if (VerifyEnabled)
|
|
MF->verify(this, "Before greedy register allocator");
|
|
|
|
RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
|
|
Indexes = &getAnalysis<SlotIndexes>();
|
|
DomTree = &getAnalysis<MachineDominatorTree>();
|
|
ReservedRegs = TRI->getReservedRegs(*MF);
|
|
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
|
|
Loops = &getAnalysis<MachineLoopInfo>();
|
|
LoopRanges = &getAnalysis<MachineLoopRanges>();
|
|
Bundles = &getAnalysis<EdgeBundles>();
|
|
SpillPlacer = &getAnalysis<SpillPlacement>();
|
|
|
|
SA.reset(new SplitAnalysis(*MF, *LIS, *Loops));
|
|
|
|
allocatePhysRegs();
|
|
addMBBLiveIns(MF);
|
|
|
|
// Run rewriter
|
|
{
|
|
NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
|
|
std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
|
|
rewriter->runOnMachineFunction(*MF, *VRM, LIS);
|
|
}
|
|
|
|
// The pass output is in VirtRegMap. Release all the transient data.
|
|
releaseMemory();
|
|
|
|
return true;
|
|
}
|