llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-20 12:31:40 +00:00

History

Quentin Colombet e817bdd304 [PeepholeOptimizer] Take advantage of the isInsertSubreg property in the

advanced copy optimization.

This is the final step patch toward transforming:
udiv    r0, r0, r2
udiv    r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov    r0, r1, d16
bx      lr

into:
udiv    r0, r0, r2
udiv    r1, r1, r3
bx      lr

Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1

and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov    r0, r1, d16

into simple generic GPR copies that the coalescer managed to remove.

<rdar://problem/12702965>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216144 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-21 00:19:16 +00:00

Analysis

Answer to Philip Reames comments

2014-08-18 22:18:14 +00:00

AsmParser

Split parseAssembly into parseAssembly and parseAssemblyInto.

2014-08-19 22:05:47 +00:00

Bitcode

BitcodeReader: Only create one basic block for each blockaddress

2014-08-16 01:54:37 +00:00

CodeGen

[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the