mirror of
https://github.com/c64scene-ar/llvm-6502.git
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11729224bf
This is a preliminary patch for fast instruction selection on PowerPC. Code generation can differ between DAG isel and fast isel. Existing tests that specify -O0 were written to expect DAG isel. Make this explicit by adding -fast-isel=false to the tests. In some cases specifying -fast-isel=false produces different code even when there isn't a fast instruction selector specified. This is because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel object exists. Thus disabling fast isel can actually produce less conservative code. Because of this, some of the expected code generation in the -O0 tests needs to be adjusted. In particular, handling of function arguments is less conservative with -fast-isel=false (see isOnlyUsedInEntryBlock() in SelectionDAGBuilder.cpp). This results in fewer stack accesses and, in some cases, reduced stack size as uselessly loaded values are no longer stored back to spill locations in the stack. No functional change with this patch; test case adjustments only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183939 91177308-0d34-0410-b5e6-96231b3b80d8
186 lines
6.0 KiB
LLVM
186 lines
6.0 KiB
LLVM
; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
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; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s
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; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
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; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
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; FIXME: When asm-parse is available, could make this an assembly test.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@ei = external global i32
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define signext i32 @test_external() nounwind {
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entry:
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%0 = load i32* @ei, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @ei, align 4
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ret i32 %0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing external variable ei.
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;
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; MEDIUM: Relocations [
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; MEDIUM: Section (2) .rela.text {
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
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;
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; LARGE: Relocations [
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; LARGE: Section (2) .rela.text {
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]]
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@test_fn_static.si = internal global i32 0, align 4
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define signext i32 @test_fn_static() nounwind {
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entry:
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%0 = load i32* @test_fn_static.si, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @test_fn_static.si, align 4
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ret i32 %0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
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; accessing function-scoped variable si.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]]
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;
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing function-scoped variable si.
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]]
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@gi = global i32 5, align 4
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define signext i32 @test_file_static() nounwind {
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entry:
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%0 = load i32* @gi, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @gi, align 4
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ret i32 %0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
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; accessing file-scope variable gi.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]]
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;
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing file-scope variable gi.
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]]
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define double @test_double_const() nounwind {
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entry:
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ret double 0x3F4FD4920B498CF0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for
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; accessing a constant.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]]
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;
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing a constant.
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]]
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define signext i32 @test_jump_table(i32 signext %i) nounwind {
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entry:
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%i.addr = alloca i32, align 4
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store i32 %i, i32* %i.addr, align 4
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%0 = load i32* %i.addr, align 4
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switch i32 %0, label %sw.default [
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i32 3, label %sw.bb
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i32 4, label %sw.bb1
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i32 5, label %sw.bb2
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i32 6, label %sw.bb3
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]
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sw.default: ; preds = %entry
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br label %sw.epilog
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sw.bb: ; preds = %entry
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%1 = load i32* %i.addr, align 4
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%mul = mul nsw i32 %1, 7
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store i32 %mul, i32* %i.addr, align 4
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br label %sw.bb1
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sw.bb1: ; preds = %entry, %sw.bb
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%2 = load i32* %i.addr, align 4
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%dec = add nsw i32 %2, -1
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store i32 %dec, i32* %i.addr, align 4
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br label %sw.bb2
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sw.bb2: ; preds = %entry, %sw.bb1
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%3 = load i32* %i.addr, align 4
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%add = add nsw i32 %3, 3
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store i32 %add, i32* %i.addr, align 4
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br label %sw.bb3
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sw.bb3: ; preds = %entry, %sw.bb2
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%4 = load i32* %i.addr, align 4
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%shl = shl i32 %4, 1
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store i32 %shl, i32* %i.addr, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb3, %sw.default
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%5 = load i32* %i.addr, align 4
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ret i32 %5
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing a jump table address.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]]
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]]
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@ti = common global i32 0, align 4
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define signext i32 @test_tentative() nounwind {
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entry:
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%0 = load i32* @ti, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @ti, align 4
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ret i32 %0
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}
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing tentatively declared variable ti.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
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define i8* @test_fnaddr() nounwind {
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entry:
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%func = alloca i32 (i32)*, align 8
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store i32 (i32)* @foo, i32 (i32)** %func, align 8
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%0 = load i32 (i32)** %func, align 8
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%1 = bitcast i32 (i32)* %0 to i8*
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ret i8* %1
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}
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declare signext i32 @foo(i32 signext)
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; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
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; accessing function address foo.
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;
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
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; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
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;
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]]
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; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]]
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