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https://github.com/c64scene-ar/llvm-6502.git
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b76f5ba103
Currently the VSX support enables use of lxvd2x and stxvd2x for 2x64 types, but does not yet use lxvw4x and stxvw4x for 4x32 types. This patch adds that support. As with lxvd2x/stxvd2x, this involves straightforward overriding of the patterns normally recognized for lvx/stvx, with preference given to the VSX patterns when VSX is enabled. In addition, the logic for permitting misaligned memory accesses is modified so that v4r32 and v4i32 are treated the same as v2f64 and v2i64 when VSX is enabled. Finally, the DAG generation for unaligned loads is changed to just use a normal LOAD (which will become lxvw4x) on P8 and later hardware, where unaligned loads are preferred over lvsl/lvx/lvx/vperm. A number of tests now generate the VSX loads/stores instead of lvx/stvx, so this patch adds VSX variants to those tests. I've also added <4 x float> tests to the vsx.ll test case, and created a vsx-p8.ll test case to be used for testing code generation for the P8Vector feature. For now, that simply tests the unaligned load/store behavior. This has been tested along with a temporary patch to enable the VSX and P8Vector features, with no new regressions encountered with or without the temporary patch applied. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220047 91177308-0d34-0410-b5e6-96231b3b80d8
32 lines
1.3 KiB
LLVM
32 lines
1.3 KiB
LLVM
; RUN: llc < %s -mcpu=pwr7 -mattr=-vsx| FileCheck %s
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; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define fastcc void @copy_to_conceal() #0 {
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entry:
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br i1 undef, label %if.then, label %if.end210
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if.then: ; preds = %entry
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br label %vector.body.i
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vector.body.i: ; preds = %vector.body.i, %if.then
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%index.i = phi i64 [ 0, %vector.body.i ], [ 0, %if.then ]
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store <8 x i16> zeroinitializer, <8 x i16>* undef, align 2
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br label %vector.body.i
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if.end210: ; preds = %entry
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ret void
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; This will generate two align-1 i64 stores. Make sure that they are
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; indexed stores and not in r+i form (which require the offset to be
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; a multiple of 4).
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; CHECK: @copy_to_conceal
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; CHECK: stdx {{[0-9]+}}, 0,
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; CHECK-VSX: @copy_to_conceal
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; CHECK-VSX: stxvw4x {{[0-9]+}}, 0,
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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