mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
70017e44cd
appropriate for targets without detailed instruction iterineries. The scheduler schedules for increased instruction level parallelism in low register pressure situation; it schedules to reduce register pressure when the register pressure becomes high. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
112 lines
4.3 KiB
C++
112 lines
4.3 KiB
C++
//===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the implementation for instruction scheduler function
|
|
// pass registry (RegisterScheduler).
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_CODEGENSCHEDULERREGISTRY_H
|
|
#define LLVM_CODEGENSCHEDULERREGISTRY_H
|
|
|
|
#include "llvm/CodeGen/MachinePassRegistry.h"
|
|
#include "llvm/Target/TargetMachine.h"
|
|
|
|
namespace llvm {
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
///
|
|
/// RegisterScheduler class - Track the registration of instruction schedulers.
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class SelectionDAGISel;
|
|
class ScheduleDAGSDNodes;
|
|
class SelectionDAG;
|
|
class MachineBasicBlock;
|
|
|
|
class RegisterScheduler : public MachinePassRegistryNode {
|
|
public:
|
|
typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
|
|
CodeGenOpt::Level);
|
|
|
|
static MachinePassRegistry Registry;
|
|
|
|
RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
|
|
: MachinePassRegistryNode(N, D, (MachinePassCtor)C)
|
|
{ Registry.Add(this); }
|
|
~RegisterScheduler() { Registry.Remove(this); }
|
|
|
|
|
|
// Accessors.
|
|
//
|
|
RegisterScheduler *getNext() const {
|
|
return (RegisterScheduler *)MachinePassRegistryNode::getNext();
|
|
}
|
|
static RegisterScheduler *getList() {
|
|
return (RegisterScheduler *)Registry.getList();
|
|
}
|
|
static FunctionPassCtor getDefault() {
|
|
return (FunctionPassCtor)Registry.getDefault();
|
|
}
|
|
static void setDefault(FunctionPassCtor C) {
|
|
Registry.setDefault((MachinePassCtor)C);
|
|
}
|
|
static void setListener(MachinePassRegistryListener *L) {
|
|
Registry.setListener(L);
|
|
}
|
|
};
|
|
|
|
/// createBURRListDAGScheduler - This creates a bottom up register usage
|
|
/// reduction list scheduler.
|
|
ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
|
|
CodeGenOpt::Level OptLevel);
|
|
|
|
/// createTDRRListDAGScheduler - This creates a top down register usage
|
|
/// reduction list scheduler.
|
|
ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
|
|
CodeGenOpt::Level OptLevel);
|
|
|
|
/// createBURRListDAGScheduler - This creates a bottom up list scheduler that
|
|
/// schedules nodes in source code order when possible.
|
|
ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
|
|
CodeGenOpt::Level OptLevel);
|
|
|
|
/// createHybridListDAGScheduler - This creates a bottom up register pressure
|
|
/// aware list scheduler that make use of latency information to avoid stalls
|
|
/// for long latency instructions in low register pressure mode. In high
|
|
/// register pressure mode it schedules to reduce register pressure.
|
|
ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
|
|
CodeGenOpt::Level);
|
|
|
|
/// createILPListDAGScheduler - This creates a bottom up register pressure
|
|
/// aware list scheduler that tries to increase instruction level parallelism
|
|
/// in low register pressure mode. In high register pressure mode it schedules
|
|
/// to reduce register pressure.
|
|
ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
|
|
CodeGenOpt::Level);
|
|
/// createTDListDAGScheduler - This creates a top-down list scheduler with
|
|
/// a hazard recognizer.
|
|
ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
|
|
CodeGenOpt::Level OptLevel);
|
|
|
|
/// createFastDAGScheduler - This creates a "fast" scheduler.
|
|
///
|
|
ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
|
|
CodeGenOpt::Level OptLevel);
|
|
|
|
/// createDefaultScheduler - This creates an instruction scheduler appropriate
|
|
/// for the target.
|
|
ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
|
|
CodeGenOpt::Level OptLevel);
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|