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184f8f7c10
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.5 KiB
LLVM
42 lines
1.5 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 -break-anti-dependencies=none | FileCheck %s
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; ModuleID = 'hh.c'
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
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target triple = "powerpc-apple-darwin9.6"
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define void @foo() nounwind {
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entry:
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; Note that part of what is being checked here is proper register reuse.
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; CHECK: mfcr [[T1:r[0-9]+]] ; cr2
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; CHECK: lis [[T2:r[0-9]+]], 1
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; CHECK: addi r3, r1, 72
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; CHECK: rotlwi [[T1]], [[T1]], 8
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; CHECK: ori [[T2]], [[T2]], 34540
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; CHECK: stwx [[T1]], r1, [[T2]]
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; CHECK: lis [[T3:r[0-9]+]], 1
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; CHECK: mfcr [[T4:r[0-9]+]] ; cr3
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; CHECK: ori [[T3]], [[T3]], 34536
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; CHECK: rotlwi [[T4]], [[T4]], 12
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; CHECK: stwx [[T4]], r1, [[T3]]
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%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
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call void @bar(i8* %x1) nounwind
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call void asm sideeffect "", "~{cr2},~{cr3}"() nounwind
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br label %return
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return: ; preds = %entry
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; CHECK: lis [[T1:r[0-9]+]], 1
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; CHECK: ori [[T1]], [[T1]], 34536
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; CHECK: lwzx [[T1]], r1, [[T1]]
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; CHECK: rotlwi [[T1]], [[T1]], 20
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; CHECK: mtcrf 16, [[T1]]
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; CHECK: lis [[T1]], 1
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; CHECK: ori [[T1]], [[T1]], 34540
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; CHECK: lwzx [[T1]], r1, [[T1]]
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; CHECK: rotlwi [[T1]], [[T1]], 24
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; CHECK: mtcrf 32, [[T1]]
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ret void
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}
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declare void @bar(i8*)
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