mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
9217916725
"Fix the MachineScheduler's logic for updating ready times for in-order. Now the scheduler updates a node's ready time as soon as it is scheduled, before releasing dependent nodes." This fix was only made in one variant of the ScheduleDAGMI driver. Francois de Ferriere reported the issue in the other bit of code where it was also needed. I never got around to coming up with a test case, but it's an obvious fix that shouldn't be delayed any longer. I'll try to refactor this code a little better. I did verify performance on a wide variety of targets and saw no negative impact with this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233366 91177308-0d34-0410-b5e6-96231b3b80d8
353 lines
13 KiB
LLVM
353 lines
13 KiB
LLVM
; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
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; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s
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; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the
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; live-interval-updating logic.
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; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -schedule-ppc-vsx-fma-mutation-early
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @test1(double %a, double %b, double %c, double %e, double* nocapture %d) #0 {
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entry:
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%0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
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store double %0, double* %d, align 8
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%1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
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%arrayidx1 = getelementptr inbounds double, double* %d, i64 1
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store double %1, double* %arrayidx1, align 8
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ret void
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; CHECK-LABEL: @test1
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; CHECK-DAG: li [[C1:[0-9]+]], 8
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; CHECK-DAG: xsmaddmdp 3, 2, 1
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; CHECK-DAG: xsmaddadp 1, 2, 4
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; CHECK-DAG: stxsdx 3, 0, 7
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; CHECK-DAG: stxsdx 1, 7, [[C1]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @test1
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; CHECK-FISL-DAG: fmr 0, 1
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; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
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; CHECK-FISL-DAG: stxsdx 0, 0, 7
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; CHECK-FISL-DAG: xsmaddadp 1, 2, 4
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8
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; CHECK-FISL-DAG: stxsdx 1, 7, [[C1]]
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; CHECK-FISL: blr
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}
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define void @test2(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
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entry:
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%0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
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store double %0, double* %d, align 8
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%1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
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%arrayidx1 = getelementptr inbounds double, double* %d, i64 1
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store double %1, double* %arrayidx1, align 8
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%2 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
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%arrayidx2 = getelementptr inbounds double, double* %d, i64 2
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store double %2, double* %arrayidx2, align 8
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ret void
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; CHECK-LABEL: @test2
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; CHECK-DAG: li [[C1:[0-9]+]], 8
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; CHECK-DAG: li [[C2:[0-9]+]], 16
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; CHECK-DAG: xsmaddmdp 3, 2, 1
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; CHECK-DAG: xsmaddmdp 4, 2, 1
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; CHECK-DAG: xsmaddadp 1, 2, 5
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; CHECK-DAG: stxsdx 3, 0, 8
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; CHECK-DAG: stxsdx 4, 8, [[C1]]
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; CHECK-DAG: stxsdx 1, 8, [[C2]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @test2
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; CHECK-FISL-DAG: fmr 0, 1
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; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
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; CHECK-FISL-DAG: stxsdx 0, 0, 8
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; CHECK-FISL-DAG: fmr 0, 1
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; CHECK-FISL-DAG: xsmaddadp 0, 2, 4
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8
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; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]]
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; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
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; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
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; CHECK-FISL: blr
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}
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define void @test3(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
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entry:
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%0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
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store double %0, double* %d, align 8
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%1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
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%2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
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%arrayidx1 = getelementptr inbounds double, double* %d, i64 3
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store double %2, double* %arrayidx1, align 8
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%3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
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%arrayidx2 = getelementptr inbounds double, double* %d, i64 2
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store double %3, double* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds double, double* %d, i64 1
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store double %1, double* %arrayidx3, align 8
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ret void
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; CHECK-LABEL: @test3
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; CHECK-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-DAG: li [[C1:[0-9]+]], 24
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; CHECK-DAG: li [[C2:[0-9]+]], 16
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; CHECK-DAG: li [[C3:[0-9]+]], 8
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; CHECK-DAG: xsmaddmdp 4, 2, 1
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; CHECK-DAG: xsmaddadp 1, 2, 5
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xsmaddadp [[F1]], 2, 3
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; CHECK-DAG: xsmaddmdp 3, 2, 4
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; CHECK-DAG: stxsdx [[F1]], 0, 8
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; CHECK-DAG: stxsdx 3, 8, [[C1]]
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; CHECK-DAG: stxsdx 1, 8, [[C2]]
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; CHECK-DAG: stxsdx 4, 8, [[C3]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @test3
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; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4
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; CHECK-FISL-DAG: fmr 4, [[F1]]
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; CHECK-FISL-DAG: xsmaddadp 4, 2, 3
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24
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; CHECK-FISL-DAG: stxsdx 4, 8, [[C1]]
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; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
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; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
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; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8
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; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]]
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; CHECK-FISL: blr
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}
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define void @test4(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
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entry:
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%0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
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store double %0, double* %d, align 8
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%1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
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%arrayidx1 = getelementptr inbounds double, double* %d, i64 1
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store double %1, double* %arrayidx1, align 8
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%2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
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%arrayidx3 = getelementptr inbounds double, double* %d, i64 3
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store double %2, double* %arrayidx3, align 8
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%3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
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%arrayidx4 = getelementptr inbounds double, double* %d, i64 2
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store double %3, double* %arrayidx4, align 8
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ret void
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; CHECK-LABEL: @test4
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; CHECK-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-DAG: li [[C1:[0-9]+]], 8
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; CHECK-DAG: li [[C2:[0-9]+]], 16
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; CHECK-DAG: xsmaddmdp 4, 2, 1
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xsmaddadp 1, 2, 5
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; CHECK-DAG: xsmaddadp [[F1]], 2, 3
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; CHECK-DAG: stxsdx [[F1]], 0, 8
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; CHECK-DAG: stxsdx 4, 8, [[C1]]
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; CHECK-DAG: li [[C3:[0-9]+]], 24
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; CHECK-DAG: xsmaddadp 4, 2, 3
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; CHECK-DAG: stxsdx 4, 8, [[C3]]
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; CHECK-DAG: stxsdx 1, 8, [[C2]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @test4
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; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 3
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; CHECK-FISL-DAG: stxsdx 0, 0, 8
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; CHECK-FISL-DAG: fmr [[F1]], 1
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; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4
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; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8
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; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]]
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; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24
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; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]]
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; CHECK-FISL-DAG: xsmaddadp 1, 2, 5
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16
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; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]]
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; CHECK-FISL: blr
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}
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declare double @llvm.fma.f64(double, double, double) #0
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define void @testv1(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double>* nocapture %d) #0 {
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entry:
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%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
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store <2 x double> %0, <2 x double>* %d, align 8
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%1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
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%arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
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store <2 x double> %1, <2 x double>* %arrayidx1, align 8
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ret void
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; CHECK-LABEL: @testv1
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; CHECK-DAG: xvmaddmdp 36, 35, 34
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; CHECK-DAG: xvmaddadp 34, 35, 37
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; CHECK-DAG: li [[C1:[0-9]+]], 16
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; CHECK-DAG: stxvd2x 36, 0, 3
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; CHECK-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @testv1
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; CHECK-FISL-DAG: xxlor 0, 34, 34
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; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
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; CHECK-FISL-DAG: stxvd2x 0, 0, 3
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; CHECK-FISL-DAG: xvmaddadp 34, 35, 37
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
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; CHECK-FISL-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]
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; CHECK-FISL: blr
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}
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define void @testv2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
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entry:
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%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
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store <2 x double> %0, <2 x double>* %d, align 8
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%1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
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%arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
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store <2 x double> %1, <2 x double>* %arrayidx1, align 8
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%2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
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%arrayidx2 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
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store <2 x double> %2, <2 x double>* %arrayidx2, align 8
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ret void
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; CHECK-LABEL: @testv2
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; CHECK-DAG: xvmaddmdp 36, 35, 34
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; CHECK-DAG: xvmaddmdp 37, 35, 34
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; CHECK-DAG: li [[C1:[0-9]+]], 16
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; CHECK-DAG: li [[C2:[0-9]+]], 32
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; CHECK-DAG: xvmaddadp 34, 35, 38
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; CHECK-DAG: stxvd2x 36, 0, 3
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; CHECK-DAG: stxvd2x 37, 3, [[C1:[0-9]+]]
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; CHECK-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @testv2
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; CHECK-FISL-DAG: xxlor 0, 34, 34
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; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
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; CHECK-FISL-DAG: stxvd2x 0, 0, 3
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; CHECK-FISL-DAG: xxlor 0, 34, 34
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; CHECK-FISL-DAG: xvmaddadp 0, 35, 37
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
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; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1:[0-9]+]]
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; CHECK-FISL-DAG: xvmaddadp 34, 35, 38
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
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; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]
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; CHECK-FISL: blr
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}
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define void @testv3(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
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entry:
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%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
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store <2 x double> %0, <2 x double>* %d, align 8
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%1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
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%2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)
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%arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 3
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store <2 x double> %2, <2 x double>* %arrayidx1, align 8
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%3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
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%arrayidx2 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
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store <2 x double> %3, <2 x double>* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
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store <2 x double> %1, <2 x double>* %arrayidx3, align 8
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ret void
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; Note: There is some unavoidable changeability in this variant. If the
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; FMAs are reordered differently, the algorithm can pick a different
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; multiplicand to destroy, changing the register assignment. There isn't
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; a good way to express this possibility, so hopefully this doesn't change
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; too often.
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; CHECK-LABEL: @testv3
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; CHECK-DAG: xxlor [[V1:[0-9]+]], 34, 34
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; CHECK-DAG: li [[C1:[0-9]+]], 48
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; CHECK-DAG: li [[C2:[0-9]+]], 32
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; CHECK-DAG: xvmaddmdp 37, 35, 34
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; CHECK-DAG: li [[C3:[0-9]+]], 16
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xvmaddadp [[V1]], 35, 36
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; CHECK-DAG: xvmaddmdp 36, 35, 37
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; CHECK-DAG: xvmaddadp 34, 35, 38
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; CHECK-DAG: stxvd2x 32, 0, 3
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; CHECK-DAG: stxvd2x 36, 3, [[C1]]
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; CHECK-DAG: stxvd2x 34, 3, [[C2]]
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; CHECK-DAG: stxvd2x 37, 3, [[C3]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @testv3
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; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34
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; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36
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; CHECK-FISL-DAG: stxvd2x [[V1]], 0, 3
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; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34
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; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37
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; CHECK-FISL-DAG: xxlor [[V3:[0-9]+]], 0, 0
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; CHECK-FISL-DAG: xvmaddadp [[V3]], 35, 36
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 48
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; CHECK-FISL-DAG: stxvd2x [[V3]], 3, [[C1]]
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; CHECK-FISL-DAG: xvmaddadp 34, 35, 38
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
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; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]]
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; CHECK-FISL-DAG: li [[C3:[0-9]+]], 16
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; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]]
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; CHECK-FISL: blr
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}
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define void @testv4(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
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entry:
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%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
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store <2 x double> %0, <2 x double>* %d, align 8
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%1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
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%arrayidx1 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 1
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store <2 x double> %1, <2 x double>* %arrayidx1, align 8
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%2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)
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%arrayidx3 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 3
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store <2 x double> %2, <2 x double>* %arrayidx3, align 8
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%3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
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%arrayidx4 = getelementptr inbounds <2 x double>, <2 x double>* %d, i64 2
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store <2 x double> %3, <2 x double>* %arrayidx4, align 8
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ret void
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; CHECK-LABEL: @testv4
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; CHECK-DAG: xxlor [[V1:[0-9]+]], 34, 34
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; CHECK-DAG: xvmaddmdp 37, 35, 34
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; CHECK-DAG: li [[C1:[0-9]+]], 16
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; CHECK-DAG: li [[C2:[0-9]+]], 32
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; CHECK-DAG: xvmaddadp 34, 35, 38
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xvmaddadp [[V1]], 35, 36
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; CHECK-DAG: stxvd2x 32, 0, 3
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; CHECK-DAG: stxvd2x 37, 3, [[C1]]
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; CHECK-DAG: li [[C3:[0-9]+]], 48
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; CHECK-DAG: xvmaddadp 37, 35, 36
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; CHECK-DAG: stxvd2x 37, 3, [[C3]]
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; CHECK-DAG: stxvd2x 34, 3, [[C2]]
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; CHECK: blr
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; CHECK-FISL-LABEL: @testv4
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; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34
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; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36
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; CHECK-FISL-DAG: stxvd2x 0, 0, 3
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; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34
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; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37
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; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16
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; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1]]
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; CHECK-FISL-DAG: xvmaddadp 0, 35, 37
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; CHECK-FISL-DAG: li [[C3:[0-9]+]], 48
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; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]]
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; CHECK-FISL-DAG: xvmaddadp 0, 35, 36
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; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32
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; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]]
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; CHECK-FISL: blr
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}
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declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) #0
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attributes #0 = { nounwind readnone }
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