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878c6281d3
The architecture doesn't really have any native v4f32 operations except v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32 elements being used. Even so, using vector registers for <4 x float> and scalarising individual operations is much better than generating completely scalar code, since there's much less register pressure. It's also more efficient to do v4f32 comparisons by extending to 2 v2f64s, comparing those, then packing the result. This particularly helps with llvmpipe. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236523 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
1.7 KiB
LLVM
62 lines
1.7 KiB
LLVM
; Test moves between FPRs and GPRs for z13 and above.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Check that moves from i32s to floats use a low GR32 and vector operation.
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define float @f1(i16 *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: llh [[REG:%r[0-5]]], 0(%r2)
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; CHECK: oilh [[REG]], 16256
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; CHECK: vlvgf %v0, [[REG]], 0
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; CHECK: br %r14
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%base = load i16, i16 *%ptr
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%ext = zext i16 %base to i32
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%full = or i32 %ext, 1065353216
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%res = bitcast i32 %full to float
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ret float %res
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}
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; Check that moves from floats to i32s use a low GR32 and vector operation.
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define void @f2(float %val, i8 *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: vlgvf [[REG:%r[0-5]]], %v0, 0
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; CHECK: stc [[REG]], 0(%r2)
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; CHECK: br %r14
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%res = bitcast float %val to i32
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%trunc = trunc i32 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; Like f2, but with a conditional store.
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define void @f3(float %val, i8 *%ptr, i32 %which) {
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; CHECK-LABEL: f3:
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; CHECK-DAG: cijlh %r3, 0,
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; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0
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; CHECK: stc [[REG]], 0(%r2)
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; CHECK: br %r14
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%int = bitcast float %val to i32
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%trunc = trunc i32 %int to i8
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%old = load i8, i8 *%ptr
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%cmp = icmp eq i32 %which, 0
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%res = select i1 %cmp, i8 %trunc, i8 %old
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store i8 %res, i8 *%ptr
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ret void
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}
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; ...and again with 16-bit memory.
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define void @f4(float %val, i16 *%ptr, i32 %which) {
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; CHECK-LABEL: f4:
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; CHECK-DAG: cijlh %r3, 0,
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; CHECK-DAG: vlgvf [[REG:%r[0-5]]], %v0, 0
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; CHECK: sth [[REG]], 0(%r2)
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; CHECK: br %r14
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%int = bitcast float %val to i32
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%trunc = trunc i32 %int to i16
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%old = load i16, i16 *%ptr
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%cmp = icmp eq i32 %which, 0
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%res = select i1 %cmp, i16 %trunc, i16 %old
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store i16 %res, i16 *%ptr
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ret void
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}
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