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llvm-6502/test/MC
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Kit Barton 948ecae20e This patch adds support for the vector quadword add/sub instructions introduced 
in POWER8:

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
In addition to adding the instructions themselves, it also adds support for the
v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and
IntrinsicEmitter.cpp).

http://reviews.llvm.org/D9081


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238144 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-25 15:49:26 +00:00
..
AArch64 [AArch64] Clean up the ELF streamer a bit. 2015-05-23 16:39:10 +00:00
ARM [AArch64] Clean up the ELF streamer a bit. 2015-05-23 16:39:10 +00:00
AsmParser Relax these tests a bit. 2015-05-22 21:37:13 +00:00
COFF Don't omit the constant when computing a cross-section relative relocation. 2015-05-14 01:10:41 +00:00
Disassembler This patch adds support for the vector quadword add/sub instructions introduced 2015-05-25 15:49:26 +00:00
ELF Produce a single string table in a ELF .o 2015-05-22 23:58:30 +00:00
Hexagon
MachO AArch64: work around ld64 bug more aggressively. 2015-05-18 22:07:20 +00:00
Markup
Mips Relax these tests a bit. 2015-05-22 21:37:13 +00:00
PowerPC This patch adds support for the vector quadword add/sub instructions introduced 2015-05-25 15:49:26 +00:00
R600
Sparc Sparc: support the "set" synthetic instruction. 2015-05-18 16:43:33 +00:00
SystemZ
X86 AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other instructions from this set 2015-05-18 06:42:57 +00:00