mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e874345be4
If pseudoToMCOpcode failed, we would return the original opcode, so operands would be swapped, but the instruction would remain the same. It resulted in LSHLREV a, b ---> LSHLREV b, a. This fixes Glamor text rendering and piglit/arb_sample_shading-builtin-gl-sample-mask on VI. This is a candidate for stable branches. v2: the test was simplified by Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240824 91177308-0d34-0410-b5e6-96231b3b80d8
392 lines
14 KiB
C++
392 lines
14 KiB
C++
//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
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#define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIDefines.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIInstrInfo : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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const TargetRegisterClass *RC,
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const MachineOperand &Op) const;
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void swapOperands(MachineBasicBlock::iterator Inst) const;
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void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst, unsigned Opcode) const;
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void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst, unsigned Opcode) const;
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void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst) const;
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void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
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MachineInstr *Inst) const;
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void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
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bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
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MachineInstr *MIb) const;
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unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
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public:
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explicit SIInstrInfo(const AMDGPUSubtarget &st);
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const SIRegisterInfo &getRegisterInfo() const override {
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return RI;
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}
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bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA) const override;
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bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1,
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int64_t &Offset2) const override;
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bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
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unsigned &Offset,
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const TargetRegisterInfo *TRI) const final;
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bool shouldClusterLoads(MachineInstr *FirstLdSt,
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MachineInstr *SecondLdSt,
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unsigned NumLoads) const final;
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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RegScavenger *RS,
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unsigned TmpReg,
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unsigned Offset,
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unsigned Size) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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// \brief Returns an opcode that can be used to move a value to a \p DstRC
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// register. If there is no hardware instruction that can store to \p
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// DstRC, then AMDGPU::COPY is returned.
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unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
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int commuteOpcode(const MachineInstr &MI) const;
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MachineInstr *commuteInstruction(MachineInstr *MI,
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bool NewMI = false) const override;
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bool findCommutedOpIndices(MachineInstr *MI,
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unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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bool isTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA = nullptr) const;
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bool areMemAccessesTriviallyDisjoint(
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MachineInstr *MIa, MachineInstr *MIb,
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AliasAnalysis *AA = nullptr) const override;
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MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg) const override;
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bool isMov(unsigned Opcode) const override;
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bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
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bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const final;
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unsigned getMachineCSELookAheadLimit() const override { return 500; }
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bool isSALU(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SALU;
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}
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bool isVALU(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VALU;
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}
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bool isSOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOP1;
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}
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bool isSOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOP2;
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}
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bool isSOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPC;
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}
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bool isSOPK(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPK;
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}
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bool isSOPP(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPP;
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}
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bool isVOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP1;
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}
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bool isVOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP2;
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}
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bool isVOP3(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP3;
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}
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bool isVOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOPC;
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}
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bool isMUBUF(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
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}
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bool isMTBUF(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
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}
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bool isSMRD(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SMRD;
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}
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bool isDS(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::DS;
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}
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bool isMIMG(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MIMG;
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}
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bool isFLAT(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::FLAT;
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}
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bool isWQM(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::WQM;
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}
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bool isVGPRSpill(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
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}
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bool isInlineConstant(const APInt &Imm) const;
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bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
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bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
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bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
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const MachineOperand &MO) const;
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/// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
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/// This function will return false if you pass it a 32-bit instruction.
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bool hasVALU32BitEncoding(unsigned Opcode) const;
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/// \brief Returns true if this operand uses the constant bus.
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bool usesConstantBus(const MachineRegisterInfo &MRI,
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const MachineOperand &MO,
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unsigned OpSize) const;
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/// \brief Return true if this instruction has any modifiers.
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/// e.g. src[012]_mod, omod, clamp.
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bool hasModifiers(unsigned Opcode) const;
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bool hasModifiersSet(const MachineInstr &MI,
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unsigned OpName) const;
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bool verifyInstruction(const MachineInstr *MI,
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StringRef &ErrInfo) const override;
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static unsigned getVALUOp(const MachineInstr &MI);
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bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
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/// \brief Return the correct register class for \p OpNo. For target-specific
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/// instructions, this will return the register class that has been defined
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/// in tablegen. For generic instructions, like REG_SEQUENCE it will return
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/// the register class of its machine operand.
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/// to infer the correct register class base on the other operands.
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const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
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unsigned OpNo) const;
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/// \brief Return the size in bytes of the operand OpNo on the given
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// instruction opcode.
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unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
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const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
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if (OpInfo.RegClass == -1) {
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// If this is an immediate operand, this must be a 32-bit literal.
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assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
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return 4;
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}
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return RI.getRegClass(OpInfo.RegClass)->getSize();
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}
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/// \brief This form should usually be preferred since it handles operands
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/// with unknown register classes.
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unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
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return getOpRegClass(MI, OpNo)->getSize();
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}
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/// \returns true if it is legal for the operand at index \p OpNo
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/// to read a VGPR.
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bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
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/// \brief Legalize the \p OpIndex operand of this instruction by inserting
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/// a MOV. For example:
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/// ADD_I32_e32 VGPR0, 15
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/// to
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/// MOV VGPR1, 15
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/// ADD_I32_e32 VGPR0, VGPR1
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///
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/// If the operand being legalized is a register, then a COPY will be used
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/// instead of MOV.
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void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
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/// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
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/// for \p MI.
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bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
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const MachineOperand *MO = nullptr) const;
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/// \brief Legalize all operands in this instruction. This function may
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/// create new instruction and insert them before \p MI.
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void legalizeOperands(MachineInstr *MI) const;
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/// \brief Split an SMRD instruction into two smaller loads of half the
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// size storing the results in \p Lo and \p Hi.
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void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
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unsigned HalfImmOp, unsigned HalfSGPROp,
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MachineInstr *&Lo, MachineInstr *&Hi) const;
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void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
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/// \brief Replace this instruction's opcode with the equivalent VALU
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/// opcode. This function will also move the users of \p MI to the
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/// VALU if necessary.
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void moveToVALU(MachineInstr &MI) const;
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unsigned calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const override;
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const TargetRegisterClass *getIndirectAddrRegClass() const override;
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MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const override;
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MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const override;
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void reserveIndirectRegisters(BitVector &Reserved,
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const MachineFunction &MF) const;
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void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
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unsigned SavReg, unsigned IndexReg) const;
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void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
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/// \brief Returns the operand named \p Op. If \p MI does not have an
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/// operand named \c Op, this function returns nullptr.
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MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
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const MachineOperand *getNamedOperand(const MachineInstr &MI,
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unsigned OpName) const {
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return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
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}
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uint64_t getDefaultRsrcDataFormat() const;
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};
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namespace AMDGPU {
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int getVOPe64(uint16_t Opcode);
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int getVOPe32(uint16_t Opcode);
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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int getAddr64Inst(uint16_t Opcode);
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int getAtomicRetOp(uint16_t Opcode);
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int getAtomicNoRetOp(uint16_t Opcode);
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const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
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const uint64_t RSRC_TID_ENABLE = 1LL << 55;
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} // End namespace AMDGPU
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namespace SI {
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namespace KernelInputOffsets {
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/// Offsets in bytes from the start of the input buffer
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enum Offsets {
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NGROUPS_X = 0,
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NGROUPS_Y = 4,
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NGROUPS_Z = 8,
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GLOBAL_SIZE_X = 12,
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GLOBAL_SIZE_Y = 16,
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GLOBAL_SIZE_Z = 20,
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LOCAL_SIZE_X = 24,
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LOCAL_SIZE_Y = 28,
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LOCAL_SIZE_Z = 32
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};
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} // End namespace KernelInputOffsets
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} // End namespace SI
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} // End namespace llvm
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#endif
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