llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-19 17:37:24 +00:00

History

Dan Gohman 8e5f2c6f65 Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8		2008-07-07 23:14:23 +00:00
..
CellSDKIntrinsics.td
Makefile
README.txt
SPU.h
SPU.td
SPUAsmPrinter.cpp
SPUCallingConv.td
SPUFrameInfo.cpp
SPUFrameInfo.h
SPUHazardRecognizers.cpp
SPUHazardRecognizers.h
SPUInstrBuilder.h
SPUInstrFormats.td
SPUInstrInfo.cpp	Pool-allocation for MachineInstrs, MachineBasicBlocks, and	2008-07-07 23:14:23 +00:00
SPUInstrInfo.h
SPUInstrInfo.td
SPUISelDAGToDAG.cpp	Add explicit keywords.	2008-07-07 18:00:37 +00:00
SPUISelLowering.cpp	Add a new getMergeValues method that does not need	2008-07-02 17:40:58 +00:00
SPUISelLowering.h
SPUMachineFunction.h	Remove attribution from file headers, per discussion on llvmdev.	2007-12-29 20:36:04 +00:00
SPUNodes.td
SPUOperands.td
SPURegisterInfo.cpp	Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating	2008-07-01 00:05:16 +00:00
SPURegisterInfo.h
SPURegisterInfo.td
SPURegisterNames.h
SPUSchedule.td
SPUSubtarget.cpp
SPUSubtarget.h
SPUTargetAsmInfo.cpp
SPUTargetAsmInfo.h
SPUTargetMachine.cpp
SPUTargetMachine.h

README.txt

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE. 

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Finish branch instructions, branch prediction

  These instructions were started, but only insofar as to get llvm-gcc-4.2's
  crtbegin.ll working (which doesn't.)

* Double floating point support

  This was started. "What's missing?" to be filled in.

* Intrinsics

  Lots of progress. "What's missing/incomplete?" to be filled in.

===-------------------------------------------------------------------------===