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opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.2 KiB
LLVM
37 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=x86_64-apple-macosx -mcpu=nocona < %s | FileCheck %s
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; After tail duplication, two copies in an early exit BB can be cancelled out.
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; rdar://10640363
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define i32 @t1(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: t1:
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; CHECK: jne
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%cmp1 = icmp eq i32 %b, 0
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br i1 %cmp1, label %while.end, label %while.body
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; CHECK: BB
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; CHECK-NOT: mov
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; CHECK: ret
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while.body: ; preds = %entry, %while.body
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%a.addr.03 = phi i32 [ %b.addr.02, %while.body ], [ %a, %entry ]
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%b.addr.02 = phi i32 [ %rem, %while.body ], [ %b, %entry ]
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%rem = srem i32 %a.addr.03, %b.addr.02
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%cmp = icmp eq i32 %rem, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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%a.addr.0.lcssa = phi i32 [ %a, %entry ], [ %b.addr.02, %while.body ]
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ret i32 %a.addr.0.lcssa
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}
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; Two movdqa (from phi-elimination) in the entry BB cancels out.
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; rdar://10428165
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define <8 x i16> @t2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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entry:
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; CHECK: t2:
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; CHECK-NOT: movdqa
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%tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
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ret <8 x i16> %tmp8
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}
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