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This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
216 lines
8.4 KiB
C++
216 lines
8.4 KiB
C++
//===- PIC16InstrInfo.cpp - PIC16 Instruction Information -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PIC16 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PIC16.h"
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#include "PIC16InstrInfo.h"
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#include "PIC16TargetMachine.h"
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#include "PIC16GenInstrInfo.inc"
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#include "llvm/Function.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cstdio>
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using namespace llvm;
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// FIXME: Add the subtarget support on this constructor.
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PIC16InstrInfo::PIC16InstrInfo(PIC16TargetMachine &tm)
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: TargetInstrInfoImpl(PIC16Insts, array_lengthof(PIC16Insts)),
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TM(tm),
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RegInfo(*this, *TM.getSubtargetImpl()) {}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot.
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/// If not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned PIC16InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == PIC16::movwf
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&& MI->getOperand(0).isReg()
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&& MI->getOperand(1).isSymbol()) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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return 0;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the dest reg along with the FrameIndex of the stack slot.
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/// If not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned PIC16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == PIC16::movf
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&& MI->getOperand(0).isReg()
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&& MI->getOperand(1).isSymbol()) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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return 0;
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}
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void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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PIC16TargetLowering *PTLI = TM.getTargetLowering();
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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const Function *Func = MBB.getParent()->getFunction();
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const std::string FuncName = Func->getName();
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const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
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// On the order of operands here: think "movwf SrcReg, tmp_slot, offset".
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if (RC == PIC16::GPRRegisterClass) {
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//MachineFunction &MF = *MBB.getParent();
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//MachineRegisterInfo &RI = MF.getRegInfo();
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BuildMI(MBB, I, DL, get(PIC16::movwf))
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.addReg(SrcReg, getKillRegState(isKill))
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.addImm(PTLI->GetTmpOffsetForFI(FI, 1))
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.addExternalSymbol(tmpName)
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.addImm(1); // Emit banksel for it.
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}
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else if (RC == PIC16::FSR16RegisterClass) {
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// This is a 16-bit register and the frameindex given by llvm is of
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// size two here. Break this index N into two zero based indexes and
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// put one into the map. The second one is always obtained by adding 1
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// to the first zero based index. In fact it is going to use 3 slots
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// as saving FSRs corrupts W also and hence we need to save/restore W also.
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unsigned opcode = (SrcReg == PIC16::FSR0) ? PIC16::save_fsr0
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: PIC16::save_fsr1;
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BuildMI(MBB, I, DL, get(opcode))
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.addReg(SrcReg, getKillRegState(isKill))
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.addImm(PTLI->GetTmpOffsetForFI(FI, 3))
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.addExternalSymbol(tmpName)
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.addImm(1); // Emit banksel for it.
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}
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else
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llvm_unreachable("Can't store this register to stack slot");
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}
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void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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PIC16TargetLowering *PTLI = TM.getTargetLowering();
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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const Function *Func = MBB.getParent()->getFunction();
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const std::string FuncName = Func->getName();
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const char *tmpName = createESName(PAN::getTempdataLabel(FuncName));
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// On the order of operands here: think "movf FrameIndex, W".
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if (RC == PIC16::GPRRegisterClass) {
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//MachineFunction &MF = *MBB.getParent();
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//MachineRegisterInfo &RI = MF.getRegInfo();
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BuildMI(MBB, I, DL, get(PIC16::movf), DestReg)
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.addImm(PTLI->GetTmpOffsetForFI(FI, 1))
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.addExternalSymbol(tmpName)
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.addImm(1); // Emit banksel for it.
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}
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else if (RC == PIC16::FSR16RegisterClass) {
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// This is a 16-bit register and the frameindex given by llvm is of
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// size two here. Break this index N into two zero based indexes and
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// put one into the map. The second one is always obtained by adding 1
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// to the first zero based index. In fact it is going to use 3 slots
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// as saving FSRs corrupts W also and hence we need to save/restore W also.
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unsigned opcode = (DestReg == PIC16::FSR0) ? PIC16::restore_fsr0
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: PIC16::restore_fsr1;
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BuildMI(MBB, I, DL, get(opcode), DestReg)
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.addImm(PTLI->GetTmpOffsetForFI(FI, 3))
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.addExternalSymbol(tmpName)
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.addImm(1); // Emit banksel for it.
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}
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else
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llvm_unreachable("Can't load this register from stack slot");
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}
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bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC == PIC16::FSR16RegisterClass) {
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BuildMI(MBB, I, DL, get(PIC16::copy_fsr), DestReg).addReg(SrcReg);
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return true;
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}
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if (DestRC == PIC16::GPRRegisterClass) {
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BuildMI(MBB, I, DL, get(PIC16::copy_w), DestReg).addReg(SrcReg);
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return true;
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}
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// Not yet supported.
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return false;
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}
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bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DestReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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SrcSubIdx = DstSubIdx = 0; // No sub-registers.
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if (MI.getOpcode() == PIC16::copy_fsr
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|| MI.getOpcode() == PIC16::copy_w) {
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DestReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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return false;
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}
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/// InsertBranch - Insert a branch into the end of the specified
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/// MachineBasicBlock. This operands to this method are the same as those
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/// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
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/// returns success and when an unconditional branch (TBB is non-null, FBB is
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/// null, Cond is empty) needs to be inserted. It returns the number of
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/// instructions inserted.
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unsigned PIC16InstrInfo::
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InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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if (FBB == 0) { // One way branch.
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if (Cond.empty()) {
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// Unconditional branch?
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DebugLoc dl = DebugLoc::getUnknownLoc();
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BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB);
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}
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return 1;
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}
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// FIXME: If the there are some conditions specified then conditional branch
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// should be generated.
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// For the time being no instruction is being generated therefore
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// returning NULL.
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return 0;
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}
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