llvm-6502/test/CodeGen/Thumb2/cortex-fp.ll
Tim Northover 2c0d42ac9a ARM: do not generate BLX instructions on Cortex-M CPUs.
Particularly on MachO, we were generating "blx _dest" instructions on M-class
CPUs, which don't actually exist. They happen to get fixed up by the linker
into valid "bl _dest" instructions (which is why such a massive issue has
remained largely undetected), but we shouldn't rely on that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214959 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-06 11:13:14 +00:00

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LLVM

; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM3
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM4
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXA8
define float @foo(float %a, float %b) {
entry:
; CHECK-LABEL: foo:
; CORTEXM3: bl ___mulsf3
; CORTEXM4: vmul.f32 s
; CORTEXA8: vmul.f32 d
%0 = fmul float %a, %b
ret float %0
}
define double @bar(double %a, double %b) {
entry:
; CHECK-LABEL: bar:
%0 = fmul double %a, %b
; CORTEXM3: bl ___muldf3
; CORTEXM4: bl ___muldf3
; CORTEXA8: vmul.f64 d
ret double %0
}