mirror of
https://github.com/c64scene-ar/llvm-6502.git
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67a6103a34
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83528 91177308-0d34-0410-b5e6-96231b3b80d8
114 lines
3.6 KiB
LLVM
114 lines
3.6 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
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;CHECK: vpaddls8:
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;CHECK: vpaddl.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
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;CHECK: vpaddls16:
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;CHECK: vpaddl.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
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;CHECK: vpaddls32:
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;CHECK: vpaddl.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
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ret <1 x i64> %tmp2
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}
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define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
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;CHECK: vpaddlu8:
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;CHECK: vpaddl.u8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
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;CHECK: vpaddlu16:
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;CHECK: vpaddl.u16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
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;CHECK: vpaddlu32:
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;CHECK: vpaddl.u32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
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ret <1 x i64> %tmp2
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}
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define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
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;CHECK: vpaddlQs8:
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;CHECK: vpaddl.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
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;CHECK: vpaddlQs16:
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;CHECK: vpaddl.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
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;CHECK: vpaddlQs32:
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;CHECK: vpaddl.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
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;CHECK: vpaddlQu8:
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;CHECK: vpaddl.u8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
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;CHECK: vpaddlQu16:
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;CHECK: vpaddl.u16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
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;CHECK: vpaddlQu32:
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;CHECK: vpaddl.u32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
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