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b46443a686
directly on the mac. This is very early, doesn't support relocations and
has a terrible hack to avoid .machine from being printed, but despite
that it generates an bitwise-identical-to-cctools .o file for stuff like
this:
define i32 @test() nounwind { ret i32 42 }
I don't plan to continue pushing this forward, but if anyone else was
interested in doing it, it should be really straight-forward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119136 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
5.2 KiB
C++
147 lines
5.2 KiB
C++
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCMCAsmInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
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if (TheTriple.getOS() == Triple::Darwin)
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return new PPCMCAsmInfoDarwin(isPPC64);
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return new PPCLinuxMCAsmInfo(isPPC64);
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}
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// This is duplicated code. Refactor this.
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static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
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MCContext &Ctx, TargetAsmBackend &TAB,
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raw_ostream &OS,
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MCCodeEmitter *Emitter,
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bool RelaxAll) {
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switch (Triple(TT).getOS()) {
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case Triple::Darwin:
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return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
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default:
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return NULL;
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}
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}
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
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RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
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RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo);
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RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo);
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// Register the MC Code Emitter
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TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
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TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterAsmBackend(ThePPC32Target, createPPCAsmBackend);
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TargetRegistry::RegisterAsmBackend(ThePPC64Target, createPPCAsmBackend);
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// Register the object streamer.
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TargetRegistry::RegisterObjectStreamer(ThePPC32Target, createMCStreamer);
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TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
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}
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PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
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const std::string &FS, bool is64Bit)
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: LLVMTargetMachine(T, TT),
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Subtarget(TT, FS, is64Bit),
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DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
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FrameInfo(Subtarget), JITInfo(*this, is64Bit),
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TLInfo(*this), TSInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()) {
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if (getRelocationModel() == Reloc::Default) {
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if (Subtarget.isDarwin())
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setRelocationModel(Reloc::DynamicNoPIC);
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else
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setRelocationModel(Reloc::Static);
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}
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}
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/// Override this for PowerPC. Tail merging happily breaks up instruction issue
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/// groups, which typically degrades performance.
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bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
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PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS)
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: PPCTargetMachine(T, TT, FS, false) {
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}
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PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
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const std::string &FS)
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: PPCTargetMachine(T, TT, FS, true) {
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Install an instruction selector.
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PM.add(createPPCISelDag(*this));
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return false;
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}
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bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Must run branch selection immediately preceding the asm printer.
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PM.add(createPPCBranchSelectionPass());
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return false;
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}
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bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
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// FIXME: This should be moved to TargetJITInfo!!
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if (Subtarget.isPPC64()) {
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// We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
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// instructions to materialize arbitrary global variable + function +
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// constant pool addresses.
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setRelocationModel(Reloc::PIC_);
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// Temporary workaround for the inability of PPC64 JIT to handle jump
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// tables.
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DisableJumpTables = true;
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} else {
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setRelocationModel(Reloc::Static);
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}
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// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
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// writing?
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Subtarget.SetJITMode();
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCJITCodeEmitterPass(*this, JCE));
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return false;
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}
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