mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f586a260ca
This consolidates code from the Hexagon, R600, and XCore targets. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.3 KiB
LLVM
36 lines
1.3 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI: @sint_to_fp64
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; SI: V_CVT_F64_I32_e32
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define void @sint_to_fp64(double addrspace(1)* %out, i32 %in) {
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%result = sitofp i32 %in to double
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store double %result, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @sint_to_fp_i1_f64:
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; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
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; FIXME: We should the VGPR sources for V_CNDMASK are copied from SGPRs,
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; we should be able to fold the SGPRs into the V_CNDMASK instructions.
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; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
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; SI: V_CNDMASK_B32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, [[CMP]]
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; SI: BUFFER_STORE_DWORDX2
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; SI: S_ENDPGM
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define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) {
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%cmp = icmp eq i32 %in, 0
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%fp = sitofp i1 %cmp to double
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store double %fp, double addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @sint_to_fp_i1_f64_load:
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; SI: V_CNDMASK_B32_e64 [[IRESULT:v[0-9]]], 0, -1
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; SI-NEXT: V_CVT_F64_I32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
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; SI: BUFFER_STORE_DWORDX2 [[RESULT]]
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; SI: S_ENDPGM
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define void @sint_to_fp_i1_f64_load(double addrspace(1)* %out, i1 %in) {
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%fp = sitofp i1 %in to double
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store double %fp, double addrspace(1)* %out, align 8
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ret void
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}
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