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https://github.com/c64scene-ar/llvm-6502.git
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bd58bdb7a6
This change adds support for the SHT_MIPS_ABIFLAGS section reading/writing to the obj2yaml and yaml2obj tools. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236738 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
1.7 KiB
YAML
64 lines
1.7 KiB
YAML
# RUN: yaml2obj -format=elf %s > %t
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# RUN: llvm-readobj -mips-abi-flags %t | FileCheck -check-prefix=OBJ %s
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# RUN: obj2yaml %t | FileCheck -check-prefix=YAML %s
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# OBJ: MIPS ABI Flags {
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# OBJ-NEXT: Version: 0
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# OBJ-NEXT: ISA: MIPS64r5
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# OBJ-NEXT: ISA Extension: Cavium Networks Octeon3 (0x13)
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# OBJ-NEXT: ASEs [ (0x103)
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# OBJ-NEXT: DSP (0x1)
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# OBJ-NEXT: DSPR2 (0x2)
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# OBJ-NEXT: VZ (0x100)
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# OBJ-NEXT: ]
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# OBJ-NEXT: FP ABI: Hard float (double precision) (0x1)
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# OBJ-NEXT: GPR size: 64
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# OBJ-NEXT: CPR1 size: 64
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# OBJ-NEXT: CPR2 size: 0
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# OBJ-NEXT: Flags 1 [ (0x1)
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# OBJ-NEXT: ODDSPREG (0x1)
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# OBJ-NEXT: ]
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# OBJ-NEXT: Flags 2: 0x0
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# OBJ-NEXT: }
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# YAML: Sections:
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# YAML-NEXT: - Name: .MIPS.abiflags
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# YAML-NEXT: Type: SHT_MIPS_ABIFLAGS
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# YAML-NEXT: AddressAlign: 0x0000000000000008
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# YAML-NEXT: ISA: MIPS64
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# YAML-NEXT: ISARevision: 0x05
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# YAML-NEXT: ISAExtension: EXT_OCTEON3
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# YAML-NEXT: ASEs: [ DSP, DSPR2, VIRT ]
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# YAML-NEXT: FpABI: FP_DOUBLE
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# YAML-NEXT: GPRSize: REG_64
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# YAML-NEXT: CPR1Size: REG_64
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# YAML-NEXT: Flags1: [ ODDSPREG ]
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FileHeader:
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Class: ELFCLASS64
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Data: ELFDATA2MSB
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Type: ET_REL
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Machine: EM_MIPS
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Sections:
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- Name: .MIPS.abiflags
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Type: SHT_MIPS_ABIFLAGS
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AddressAlign: 8
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Version: 0
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ISA: MIPS64
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ISARevision: 5
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ISAExtension: EXT_OCTEON3
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ASEs: [ DSP, DSPR2, VIRT ]
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FpABI: FP_DOUBLE
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GPRSize: REG_64
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CPR1Size: REG_64
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CPR2Size: REG_NONE
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Flags1: [ ODDSPREG ]
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Flags2: 0x0
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Symbols:
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Local:
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- Name: .MIPS.abiflags
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Type: STT_SECTION
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Section: .MIPS.abiflags
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