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https://github.com/c64scene-ar/llvm-6502.git
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e921f32353
The long encoding for Thumb2 unconditional branches is broken. Additionally, there is no range checking for target operands; as such for instructions originating in assembly code, only short Thumb encodings are generated, regardless of the bitsize needed for the offset. Adding range checking is non trivial due to the representation of Thumb branch instructions. There is no true difference between conditional and unconditional branches in terms of operands and syntax - even unconditional branches have a predicate which is expected to match that of the IT block they are in. Yet, the encodings and the permitted size of the offset differ. Due to this, for any mnemonic there are really 4 encodings to choose for. The problem cannot be handled in the parser alone or by manipulating td files. Because the parser builds first a set of match candidates and then checks them one by one, whatever tablegen-only solution might be found will ultimately be dependent of the parser's evaluation order. What's worse is that due to the fact that all branches have the same syntax and the same kinds of operands, that order is governed by the lexicographical ordering of the names of operand classes... To circumvent all this, any necessary disambiguation is added to the instruction validation pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
183 lines
6.0 KiB
ArmAsm
183 lines
6.0 KiB
ArmAsm
@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s
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@ Check for various assembly diagnostic messages on invalid input.
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@ ADD instruction w/o 'S' suffix.
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add r1, r2, r3
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@ CHECK-ERRORS: error: invalid instruction
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@ CHECK-ERRORS: add r1, r2, r3
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@ CHECK-ERRORS: ^
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@ Instructions which require v6+ for both registers to be low regs.
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add r2, r3
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mov r2, r3
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@ CHECK-ERRORS: error: instruction variant requires Thumb2
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@ CHECK-ERRORS: add r2, r3
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later
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@ CHECK-ERRORS-V5: mov r2, r3
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@ CHECK-ERRORS-V5: ^
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@ Out of range immediates for ASR instruction.
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asrs r2, r3, #33
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: asrs r2, r3, #33
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@ CHECK-ERRORS: ^
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@ Out of range immediates for BKPT instruction.
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bkpt #256
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bkpt #-1
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error: invalid operand for instruction
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bkpt #256
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^
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error: invalid operand for instruction
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bkpt #-1
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^
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@ Invalid writeback and register lists for LDM
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ldm r2!, {r5, r8}
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ldm r2, {r5, r7}
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ldm r2!, {r2, r3, r4}
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: ldm r2!, {r5, r8}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: writeback operator '!' expected
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@ CHECK-ERRORS: ldm r2, {r5, r7}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
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@ CHECK-ERRORS: ldm r2!, {r2, r3, r4}
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@ CHECK-ERRORS: ^
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@ Invalid writeback and register lists for PUSH/POP
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pop {r1, r2, r10}
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push {r8, r9}
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@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc
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@ CHECK-ERRORS: pop {r1, r2, r10}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr
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@ CHECK-ERRORS: push {r8, r9}
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@ CHECK-ERRORS: ^
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@ Invalid writeback and register lists for STM
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stm r1, {r2, r6}
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stm r1!, {r2, r9}
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: stm r1, {r2, r6}
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: registers must be in range r0-r7
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@ CHECK-ERRORS: stm r1!, {r2, r9}
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@ CHECK-ERRORS: ^
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@ Out of range immediates for LSL instruction.
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lsls r4, r5, #-1
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lsls r4, r5, #32
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: lsls r4, r5, #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: lsls r4, r5, #32
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@ CHECK-ERRORS: ^
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@ Mismatched source/destination operands for MUL instruction.
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muls r1, r2, r3
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@ CHECK-ERRORS: error: destination register must match source register
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@ CHECK-ERRORS: muls r1, r2, r3
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@ CHECK-ERRORS: ^
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@ Out of range immediates for STR instruction.
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str r2, [r7, #-1]
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str r5, [r1, #3]
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str r3, [r7, #128]
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: str r2, [r7, #-1]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: str r5, [r1, #3]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: str r3, [r7, #128]
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@ CHECK-ERRORS: ^
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@ Out of range immediate for SVC instruction.
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svc #-1
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svc #256
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: svc #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: arm-mode
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@ CHECK-ERRORS: svc #256
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@ CHECK-ERRORS: ^
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@ Out of range immediate for ADD SP instructions
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add sp, #-1
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add sp, #3
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add sp, sp, #512
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add r2, sp, #1024
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: add sp, #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: add sp, #3
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: add sp, sp, #512
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: arm-mode
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@ CHECK-ERRORS: add r2, sp, #1024
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@ CHECK-ERRORS: ^
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add r2, sp, ip
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@ CHECK-ERRORS: error: source register must be the same as destination
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@ CHECK-ERRORS: add r2, sp, ip
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@ CHECK-ERRORS: ^
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@------------------------------------------------------------------------------
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@ WFE/WFI/YIELD - out of range immediates for Thumb1 branches
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@------------------------------------------------------------------------------
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beq #-258
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bne #256
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bgt #13
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b #-1048578
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b #1048576
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b #10323
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@ CHECK-ERRORS: error: Branch target out of range
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@ CHECK-ERRORS: error: Branch target out of range
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@ CHECK-ERRORS: error: Branch target out of range
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@ CHECK-ERRORS: error: Branch target out of range
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@ CHECK-ERRORS: error: Branch target out of range
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@ CHECK-ERRORS: error: Branch target out of range
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@------------------------------------------------------------------------------
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@ WFE/WFI/YIELD - are not supported pre v6T2
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@------------------------------------------------------------------------------
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wfe
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wfi
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yield
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: wfe
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: wfi
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: instruction requires: thumb2
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@ CHECK-ERRORS: yield
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@ CHECK-ERRORS: ^
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@------------------------------------------------------------------------------
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@ PLDW required mp-extensions
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@------------------------------------------------------------------------------
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pldw [r0, #4]
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@ CHECK-ERRORS: error: instruction requires: mp-extensions
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