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https://github.com/c64scene-ar/llvm-6502.git
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b191e0ab51
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31312 91177308-0d34-0410-b5e6-96231b3b80d8
235 lines
7.8 KiB
C++
235 lines
7.8 KiB
C++
//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMRegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Type.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/STLExtras.h"
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#include <iostream>
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using namespace llvm;
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(const MachineFunction &MF) {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return NoFramePointerElim || MFI->hasVarSizedObjects();
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}
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ARMRegisterInfo::ARMRegisterInfo()
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: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
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}
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void ARMRegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FI,
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const TargetRegisterClass *RC) const {
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assert (RC == ARM::IntRegsRegisterClass);
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BuildMI(MBB, I, ARM::str, 3).addReg(SrcReg).addImm(0).addFrameIndex(FI);
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}
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void ARMRegisterInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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assert (RC == ARM::IntRegsRegisterClass);
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BuildMI(MBB, I, ARM::ldr, 2, DestReg).addImm(0).addFrameIndex(FI);
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}
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void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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assert(RC == ARM::IntRegsRegisterClass ||
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RC == ARM::FPRegsRegisterClass ||
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RC == ARM::DFPRegsRegisterClass);
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if (RC == ARM::IntRegsRegisterClass)
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BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
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.addImm(ARMShift::LSL);
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else if (RC == ARM::FPRegsRegisterClass)
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BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
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else
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BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
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}
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MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
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unsigned OpNum,
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int FI) const {
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return NULL;
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}
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const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = {
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R9, ARM::R10, ARM::R11,
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ARM::R14, 0
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};
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return CalleeSaveRegs;
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}
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const TargetRegisterClass* const *
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ARMRegisterInfo::getCalleeSaveRegClasses() const {
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static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
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&ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
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&ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass, &ARM::IntRegsRegClass,
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&ARM::IntRegsRegClass, 0
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};
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return CalleeSaveRegClasses;
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}
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void ARMRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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MachineInstr *Old = I;
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
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// sub sp, sp, amount
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BuildMI(MBB, I, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
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.addImm(0).addImm(ARMShift::LSL);
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} else {
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// add sp, sp, amount
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assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
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BuildMI(MBB, I, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
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.addImm(0).addImm(ARMShift::LSL);
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}
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}
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}
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MBB.erase(I);
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}
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void
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ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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assert (MI.getOpcode() == ARM::ldr ||
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MI.getOpcode() == ARM::str ||
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MI.getOpcode() == ARM::lea_addri);
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unsigned FrameIdx = 2;
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unsigned OffIdx = 1;
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int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(OffIdx).getImmedValue();
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unsigned StackSize = MF.getFrameInfo()->getStackSize();
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Offset += StackSize;
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assert (Offset >= 0);
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unsigned BaseRegister = hasFP(MF) ? ARM::R11 : ARM::R13;
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if (Offset < 4096) {
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// Replace the FrameIndex with r13
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MI.getOperand(FrameIdx).ChangeToRegister(BaseRegister, false);
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// Replace the ldr offset with Offset
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MI.getOperand(OffIdx).ChangeToImmediate(Offset);
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} else {
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// Insert a set of r12 with the full address
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// r12 = r13 + offset
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MachineBasicBlock *MBB2 = MI.getParent();
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BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(BaseRegister)
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.addImm(Offset).addImm(0).addImm(ARMShift::LSL);
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// Replace the FrameIndex with r12
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MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
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}
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}
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void ARMRegisterInfo::
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
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void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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int NumBytes = (int) MFI->getStackSize();
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bool HasFP = hasFP(MF);
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if (MFI->hasCalls()) {
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// We reserve argument space for call sites in the function immediately on
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// entry to the current function. This eliminates the need for add/sub
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// brackets around call sites.
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NumBytes += MFI->getMaxCallFrameSize();
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}
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if (HasFP)
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// Add space for storing the FP
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NumBytes += 4;
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// Align to 8 bytes
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NumBytes = ((NumBytes + 7) / 8) * 8;
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MFI->setStackSize(NumBytes);
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//sub sp, sp, #NumBytes
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BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
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.addImm(0).addImm(ARMShift::LSL);
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if (HasFP) {
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BuildMI(MBB, MBBI, ARM::str, 3)
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.addReg(ARM::R11).addImm(0).addReg(ARM::R13);
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BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
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addImm(ARMShift::LSL);
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}
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}
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void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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assert(MBBI->getOpcode() == ARM::bx &&
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"Can only insert epilog into returning blocks");
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MachineFrameInfo *MFI = MF.getFrameInfo();
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int NumBytes = (int) MFI->getStackSize();
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if (hasFP(MF)) {
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BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
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addImm(ARMShift::LSL);
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BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R11).addImm(0).addReg(ARM::R13);
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}
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//add sp, sp, #NumBytes
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BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
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.addImm(0).addImm(ARMShift::LSL);
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}
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unsigned ARMRegisterInfo::getRARegister() const {
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return ARM::R14;
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}
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unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
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return hasFP(MF) ? ARM::R11 : ARM::R13;
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}
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#include "ARMGenRegisterInfo.inc"
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