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https://github.com/c64scene-ar/llvm-6502.git
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1d09d56fe1
This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
152 lines
5.3 KiB
C++
152 lines
5.3 KiB
C++
//===-- SystemZMCAsmBackend.cpp - SystemZ assembler backend ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SystemZMCTargetDesc.h"
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#include "MCTargetDesc/SystemZMCFixups.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCObjectWriter.h"
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using namespace llvm;
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// Value is a fully-resolved relocation value: Symbol + Addend [- Pivot].
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// Return the bits that should be installed in a relocation field for
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// fixup kind Kind.
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static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value) {
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if (Kind < FirstTargetFixupKind)
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return Value;
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switch (unsigned(Kind)) {
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case SystemZ::FK_390_PC16DBL:
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case SystemZ::FK_390_PC32DBL:
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case SystemZ::FK_390_PLT16DBL:
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case SystemZ::FK_390_PLT32DBL:
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return (int64_t)Value / 2;
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}
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llvm_unreachable("Unknown fixup kind!");
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}
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// If Opcode can be relaxed, return the relaxed form, otherwise return 0.
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static unsigned getRelaxedOpcode(unsigned Opcode) {
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switch (Opcode) {
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case SystemZ::BRC: return SystemZ::BRCL;
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case SystemZ::J: return SystemZ::JG;
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case SystemZ::BRAS: return SystemZ::BRASL;
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}
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return 0;
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}
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namespace {
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class SystemZMCAsmBackend : public MCAsmBackend {
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uint8_t OSABI;
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public:
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SystemZMCAsmBackend(uint8_t osABI)
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: OSABI(osABI) {}
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// Override MCAsmBackend
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virtual unsigned getNumFixupKinds() const LLVM_OVERRIDE {
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return SystemZ::NumTargetFixupKinds;
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}
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virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const
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LLVM_OVERRIDE;
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virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const LLVM_OVERRIDE;
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virtual bool mayNeedRelaxation(const MCInst &Inst) const LLVM_OVERRIDE;
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virtual bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *Fragment,
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const MCAsmLayout &Layout) const
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LLVM_OVERRIDE;
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virtual void relaxInstruction(const MCInst &Inst,
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MCInst &Res) const LLVM_OVERRIDE;
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virtual bool writeNopData(uint64_t Count,
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MCObjectWriter *OW) const LLVM_OVERRIDE;
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virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const
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LLVM_OVERRIDE {
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return createSystemZObjectWriter(OS, OSABI);
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}
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virtual bool doesSectionRequireSymbols(const MCSection &Section) const
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LLVM_OVERRIDE {
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return false;
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}
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};
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} // end anonymous namespace
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const MCFixupKindInfo &
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SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[SystemZ::NumTargetFixupKinds] = {
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{ "FK_390_PC16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "FK_390_PC32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
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{ "FK_390_PLT16DBL", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "FK_390_PLT32DBL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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void SystemZMCAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value) const {
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MCFixupKind Kind = Fixup.getKind();
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unsigned Offset = Fixup.getOffset();
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unsigned Size = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
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assert(Offset + Size <= DataSize && "Invalid fixup offset!");
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// Big-endian insertion of Size bytes.
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Value = extractBitsForFixup(Kind, Value);
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unsigned ShiftValue = (Size * 8) - 8;
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for (unsigned I = 0; I != Size; ++I) {
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Data[Offset + I] |= uint8_t(Value >> ShiftValue);
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ShiftValue -= 8;
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}
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}
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bool SystemZMCAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
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return getRelaxedOpcode(Inst.getOpcode()) != 0;
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}
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bool
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SystemZMCAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *Fragment,
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const MCAsmLayout &Layout) const {
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// At the moment we just need to relax 16-bit fields to wider fields.
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Value = extractBitsForFixup(Fixup.getKind(), Value);
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return (int16_t)Value != (int64_t)Value;
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}
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void SystemZMCAsmBackend::relaxInstruction(const MCInst &Inst,
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MCInst &Res) const {
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unsigned Opcode = getRelaxedOpcode(Inst.getOpcode());
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assert(Opcode && "Unexpected insn to relax");
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Res = Inst;
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Res.setOpcode(Opcode);
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}
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bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
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MCObjectWriter *OW) const {
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for (uint64_t I = 0; I != Count; ++I)
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OW->Write8(7);
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return true;
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}
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MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, StringRef TT,
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StringRef CPU) {
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
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return new SystemZMCAsmBackend(OSABI);
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}
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