llvm-6502/test/CodeGen
James Y Knight 8eb1aaac9c [SPARC] Cleanup handling of the Y/ASR registers.
- Implement copying ASR to/from GPR regs.
- Mark ASRs as non-allocatable, so it won't try to arbitrarily use
  them inappropriately.
- Instead of inserting explicit WRASR/RDASR nodes in the MUL/DIV
  routines, just do normal register copies.
- Also...mark div as using Y, not just writing it.

Added a test case with some code which previously died with an
assertion failure (with -O0), or produced wrong code (otherwise).

(Third time's the charm?)

Differential Revision: http://reviews.llvm.org/D10401

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241686 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-08 16:25:12 +00:00
..
AArch64 Add more nvcasts 2015-07-07 23:13:18 +00:00
AMDGPU
ARM Fix test case to unbreak build. 2015-07-07 14:45:12 +00:00
BPF
CPP
Generic
Hexagon [Hexagon] Generate "insert" instructions more aggressively 2015-07-08 14:47:34 +00:00
Inputs
Mips
MIR MIR Serialization: Serialize the 'dead' register machine operand flag. 2015-07-07 20:34:53 +00:00
MSP430
NVPTX
PowerPC
SPARC [SPARC] Cleanup handling of the Y/ASR registers. 2015-07-08 16:25:12 +00:00
SystemZ
Thumb
Thumb2
WebAssembly [WebAssembly] Create a CodeGen unittest directory. 2015-07-06 23:14:57 +00:00
WinEH [WinEH] Add localaddress intrinsic instead of using frameaddress 2015-07-07 23:23:03 +00:00
X86 [X86][SSE] Added (V)ROUNDSD + (V)ROUNDSS stack folding support 2015-07-08 08:07:57 +00:00
XCore