Matthias Braun e942914d29 ARM: Thumb2 LDRD/STRD supports independent input/output regs ... The existing code would unnecessarily break LDRD/STRD apart with non-adjacent registers, on thumb2 this is not necessary. Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore as there is not reason to set register hints anymore, changing that is something for a future patch however. Differential Revision: http://reviews.llvm.org/D9694 Recommiting after the revert in r238821, the buildbot still failed with the patch removed so there seems to be another reason for the breakage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238935 91177308-0d34-0410-b5e6-96231b3b80d8		2015-06-03 16:30:24 +00:00
..
AArch64	AArch64: Use CMP;CCMP sequences for and/or/setcc trees.	2015-06-01 22:31:17 +00:00
ARM	ARM: Thumb2 LDRD/STRD supports independent input/output regs	2015-06-03 16:30:24 +00:00
BPF
CPP
Generic	Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).	2015-05-27 18:02:19 +00:00
Hexagon	Revert "[Hexagon] Adding basic ELF relocation generation and testing advanced relaxation codepath."	2015-06-01 19:20:47 +00:00
Inputs
Mips	[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.	2015-06-02 20:32:50 +00:00
MIR	MIR Serialization: use correct line and column numbers for LLVM IR errors.	2015-05-29 17:05:41 +00:00
MSP430
NVPTX	[NVPTXFavorNonGenericAddrSpaces] recursively trace into GEP and BitCast	2015-05-29 17:00:27 +00:00
PowerPC	Add support for VSX FMA single-precision instructions to the PPC back end	2015-05-29 17:13:25 +00:00
R600	LiveRangeEdit: Fix liveranges not shrinking on subrange kill.	2015-06-01 21:26:26 +00:00
SPARC
SystemZ
Thumb	Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM.	2015-05-28 20:02:45 +00:00
Thumb2	ARM: Thumb2 LDRD/STRD supports independent input/output regs	2015-06-03 16:30:24 +00:00
WinEH
X86	re-apply 238809	2015-06-03 13:41:48 +00:00
XCore