mirror of
https://github.com/c64scene-ar/llvm-6502.git
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19254c49a8
This moves the bit twiddling and string fiddling functions required by other parts of the backend into a separate library. Previously they resided in AArch64Desc, which created a circular dependency between various components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174369 91177308-0d34-0410-b5e6-96231b3b80d8
141 lines
4.6 KiB
C++
141 lines
4.6 KiB
C++
//===-- AArch64MCInstLower.cpp - Convert AArch64 MachineInstr to an MCInst -==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower AArch64 MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64AsmPrinter.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64MCExpr.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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MCOperand
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AArch64AsmPrinter::lowerSymbolOperand(const MachineOperand &MO,
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const MCSymbol *Sym) const {
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const MCExpr *Expr = 0;
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Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, OutContext);
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switch (MO.getTargetFlags()) {
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case AArch64II::MO_GOT:
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Expr = AArch64MCExpr::CreateGOT(Expr, OutContext);
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break;
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case AArch64II::MO_GOT_LO12:
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Expr = AArch64MCExpr::CreateGOTLo12(Expr, OutContext);
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break;
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case AArch64II::MO_LO12:
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Expr = AArch64MCExpr::CreateLo12(Expr, OutContext);
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break;
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case AArch64II::MO_DTPREL_G1:
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Expr = AArch64MCExpr::CreateDTPREL_G1(Expr, OutContext);
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break;
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case AArch64II::MO_DTPREL_G0_NC:
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Expr = AArch64MCExpr::CreateDTPREL_G0_NC(Expr, OutContext);
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break;
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case AArch64II::MO_GOTTPREL:
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Expr = AArch64MCExpr::CreateGOTTPREL(Expr, OutContext);
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break;
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case AArch64II::MO_GOTTPREL_LO12:
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Expr = AArch64MCExpr::CreateGOTTPRELLo12(Expr, OutContext);
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break;
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case AArch64II::MO_TLSDESC:
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Expr = AArch64MCExpr::CreateTLSDesc(Expr, OutContext);
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break;
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case AArch64II::MO_TLSDESC_LO12:
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Expr = AArch64MCExpr::CreateTLSDescLo12(Expr, OutContext);
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break;
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case AArch64II::MO_TPREL_G1:
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Expr = AArch64MCExpr::CreateTPREL_G1(Expr, OutContext);
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break;
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case AArch64II::MO_TPREL_G0_NC:
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Expr = AArch64MCExpr::CreateTPREL_G0_NC(Expr, OutContext);
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break;
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case AArch64II::MO_NO_FLAG:
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// Expr is already correct
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break;
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default:
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llvm_unreachable("Unexpected MachineOperand flag");
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}
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if (!MO.isJTI() && MO.getOffset())
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Expr = MCBinaryExpr::CreateAdd(Expr,
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MCConstantExpr::Create(MO.getOffset(),
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OutContext),
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OutContext);
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return MCOperand::CreateExpr(Expr);
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}
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bool AArch64AsmPrinter::lowerOperand(const MachineOperand &MO,
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MCOperand &MCOp) const {
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switch (MO.getType()) {
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default: llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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if (MO.isImplicit())
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return false;
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assert(!MO.getSubReg() && "Subregs should be eliminated!");
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MCOp = MCOperand::CreateReg(MO.getReg());
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break;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::CreateImm(MO.getImm());
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = lowerSymbolOperand(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = lowerSymbolOperand(MO, GetExternalSymbolSymbol(MO.getSymbolName()));
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = lowerSymbolOperand(MO, Mang->getSymbol(MO.getGlobal()));
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
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MO.getMBB()->getSymbol(), OutContext));
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = lowerSymbolOperand(MO, GetJTISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = lowerSymbolOperand(MO, GetCPISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_RegisterMask:
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// Ignore call clobbers
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return false;
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}
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return true;
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}
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void llvm::LowerAArch64MachineInstrToMCInst(const MachineInstr *MI,
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MCInst &OutMI,
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AArch64AsmPrinter &AP) {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp;
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if (AP.lowerOperand(MO, MCOp))
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OutMI.addOperand(MCOp);
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}
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}
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