Weiming Zhao 0449d522a6 Folding into CSEL when there is ZEXT between SETCC and ADD ... Normally, patterns like (add x, (setcc cc ...)) will be folded into (csel x, x+1, not cc). However, if there is a ZEXT after SETCC, they won't be folded. This patch recognizes the ZEXT and allows the generation of CSINC. This patch fixes bug 19680. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208660 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-13 00:40:58 +00:00
..
AArch64	TableGen: use PrintMethods to print more aliases	2014-05-12 18:04:06 +00:00
ARM	Fix ARM bswap16.ll test on Windows	2014-05-12 22:13:07 +00:00
ARM64	Folding into CSEL when there is ZEXT between SETCC and ADD	2014-05-13 00:40:58 +00:00
CPP
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon
Inputs
Mips	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
MSP430
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC	[PowerPC] Add global named register support	2014-05-11 19:29:11 +00:00
R600	R600: Add mul24 intrinsics	2014-05-12 17:49:57 +00:00
SPARC	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
SystemZ
Thumb
Thumb2
X86	Try to fix an SDAG dependence issue with sret	2014-05-12 22:01:27 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00