mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
181 lines
6.4 KiB
LLVM
181 lines
6.4 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vpaddi8:
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;CHECK: vpadd.i8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vpaddi16:
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;CHECK: vpadd.i16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vpaddi32:
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;CHECK: vpadd.i32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vpaddf32:
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;CHECK: vpadd.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x float> %tmp3
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}
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declare <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
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define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vpaddls8:
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;CHECK: vpaddl.s8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vpaddls16:
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;CHECK: vpaddl.s16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vpaddls32:
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;CHECK: vpaddl.s32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
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ret <1 x i64> %tmp2
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}
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define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vpaddlu8:
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;CHECK: vpaddl.u8
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vpaddlu16:
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;CHECK: vpaddl.u16
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vpaddlu32:
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;CHECK: vpaddl.u32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
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ret <1 x i64> %tmp2
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}
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define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: vpaddlQs8:
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;CHECK: vpaddl.s8
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vpaddlQs16:
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;CHECK: vpaddl.s16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vpaddlQs32:
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;CHECK: vpaddl.s32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
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;CHECK-LABEL: vpaddlQu8:
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;CHECK: vpaddl.u8
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vpaddlQu16:
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;CHECK: vpaddl.u16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vpaddlQu32:
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;CHECK: vpaddl.u32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
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ret <2 x i64> %tmp2
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}
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; Test AddCombine optimization that generates a vpaddl.s
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define void @addCombineToVPADDL() nounwind ssp {
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; CHECK: vpaddl.s8
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%cbcr = alloca <16 x i8>, align 16
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%X = alloca <8 x i8>, align 8
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%tmp = load <16 x i8>, <16 x i8>* %cbcr
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%tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%tmp2 = load <16 x i8>, <16 x i8>* %cbcr
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%tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%add = add <8 x i8> %tmp3, %tmp1
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store <8 x i8> %add, <8 x i8>* %X, align 8
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ret void
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}
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; Legalization produces a EXTRACT_VECTOR_ELT DAG node which performs an extend from
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; i16 to i32. In this case the input for the formed VPADDL needs to be a vector of i16s.
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define <2 x i16> @fromExtendingExtractVectorElt(<4 x i16> %in) {
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;CHECK-LABEL: fromExtendingExtractVectorElt:
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;CHECK: vpaddl.s16
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%tmp1 = shufflevector <4 x i16> %in, <4 x i16> undef, <2 x i32> <i32 0, i32 2>
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%tmp2 = shufflevector <4 x i16> %in, <4 x i16> undef, <2 x i32> <i32 1, i32 3>
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%x = add <2 x i16> %tmp2, %tmp1
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ret <2 x i16> %x
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}
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declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32>) nounwind readnone
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