mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
3.4 KiB
LLVM
91 lines
3.4 KiB
LLVM
; RUN: llc -mtriple=x86_64-linux -mcpu=nehalem < %s | FileCheck %s --check-prefix=LIN
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; RUN: llc -mtriple=x86_64-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=WIN
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; RUN: llc -mtriple=i686-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=LIN32
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; rdar://7398554
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; When doing vector gather-scatter index calculation with 32-bit indices,
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; use an efficient mov/shift sequence rather than shuffling each individual
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; element out of the index vector.
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; CHECK-LABEL: foo:
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; LIN: movdqa (%rsi), %xmm0
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; LIN: pand (%rdx), %xmm0
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; LIN: pextrq $1, %xmm0, %r[[REG4:.+]]
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; LIN: movd %xmm0, %r[[REG2:.+]]
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; LIN: movslq %e[[REG2]], %r[[REG1:.+]]
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; LIN: sarq $32, %r[[REG2]]
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; LIN: movslq %e[[REG4]], %r[[REG3:.+]]
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; LIN: sarq $32, %r[[REG4]]
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; LIN: movsd (%rdi,%r[[REG1]],8), %xmm0
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; LIN: movhpd (%rdi,%r[[REG2]],8), %xmm0
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; LIN: movsd (%rdi,%r[[REG3]],8), %xmm1
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; LIN: movhpd (%rdi,%r[[REG4]],8), %xmm1
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; WIN: movdqa (%rdx), %xmm0
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; WIN: pand (%r8), %xmm0
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; WIN: pextrq $1, %xmm0, %r[[REG4:.+]]
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; WIN: movd %xmm0, %r[[REG2:.+]]
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; WIN: movslq %e[[REG2]], %r[[REG1:.+]]
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; WIN: sarq $32, %r[[REG2]]
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; WIN: movslq %e[[REG4]], %r[[REG3:.+]]
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; WIN: sarq $32, %r[[REG4]]
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; WIN: movsd (%rcx,%r[[REG1]],8), %xmm0
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; WIN: movhpd (%rcx,%r[[REG2]],8), %xmm0
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; WIN: movsd (%rcx,%r[[REG3]],8), %xmm1
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; WIN: movhpd (%rcx,%r[[REG4]],8), %xmm1
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define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind {
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%a = load <4 x i32>, <4 x i32>* %i
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%b = load <4 x i32>, <4 x i32>* %h
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%j = and <4 x i32> %a, %b
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%d0 = extractelement <4 x i32> %j, i32 0
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%d1 = extractelement <4 x i32> %j, i32 1
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%d2 = extractelement <4 x i32> %j, i32 2
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%d3 = extractelement <4 x i32> %j, i32 3
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%q0 = getelementptr double, double* %p, i32 %d0
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%q1 = getelementptr double, double* %p, i32 %d1
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%q2 = getelementptr double, double* %p, i32 %d2
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%q3 = getelementptr double, double* %p, i32 %d3
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%r0 = load double, double* %q0
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%r1 = load double, double* %q1
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%r2 = load double, double* %q2
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%r3 = load double, double* %q3
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%v0 = insertelement <4 x double> undef, double %r0, i32 0
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%v1 = insertelement <4 x double> %v0, double %r1, i32 1
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%v2 = insertelement <4 x double> %v1, double %r2, i32 2
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%v3 = insertelement <4 x double> %v2, double %r3, i32 3
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ret <4 x double> %v3
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}
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; Check that the sequence previously used above, which bounces the vector off the
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; cache works for x86-32. Note that in this case it will not be used for index
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; calculation, since indexes are 32-bit, not 64.
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; CHECK-LABEL: old:
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; LIN32: movaps %xmm0, (%esp)
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; LIN32-DAG: {{(mov|and)}}l (%esp),
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; LIN32-DAG: {{(mov|and)}}l 4(%esp),
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; LIN32-DAG: {{(mov|and)}}l 8(%esp),
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; LIN32-DAG: {{(mov|and)}}l 12(%esp),
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define <4 x i64> @old(double* %p, <4 x i32>* %i, <4 x i32>* %h, i64 %f) nounwind {
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%a = load <4 x i32>, <4 x i32>* %i
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%b = load <4 x i32>, <4 x i32>* %h
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%j = and <4 x i32> %a, %b
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%d0 = extractelement <4 x i32> %j, i32 0
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%d1 = extractelement <4 x i32> %j, i32 1
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%d2 = extractelement <4 x i32> %j, i32 2
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%d3 = extractelement <4 x i32> %j, i32 3
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%q0 = zext i32 %d0 to i64
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%q1 = zext i32 %d1 to i64
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%q2 = zext i32 %d2 to i64
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%q3 = zext i32 %d3 to i64
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%r0 = and i64 %q0, %f
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%r1 = and i64 %q1, %f
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%r2 = and i64 %q2, %f
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%r3 = and i64 %q3, %f
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%v0 = insertelement <4 x i64> undef, i64 %r0, i32 0
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%v1 = insertelement <4 x i64> %v0, i64 %r1, i32 1
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%v2 = insertelement <4 x i64> %v1, i64 %r2, i32 2
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%v3 = insertelement <4 x i64> %v2, i64 %r3, i32 3
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ret <4 x i64> %v3
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}
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