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30b5412d92
Summary: The contents of the HI/LO registers are unpredictable after the execution of the MUL instruction. In addition to implicitly defining these registers in the MUL instruction definition, we have to mark those registers as dead too. Without this the fast register allocator is running out of registers when the MUL instruction is followed by another one that tries to allocate the AC0 register. Based on a patch by Reed Kotler. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D9825 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238755 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
617 B
LLVM
19 lines
617 B
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 \
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; RUN: -fast-isel -mips-fast-isel -relocation-model=pic
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 \
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; RUN: -fast-isel -mips-fast-isel -relocation-model=pic
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; The test is just to make sure it is able to allocate
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; registers for this example. There was an issue with allocating AC0
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; after a mul instruction.
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declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
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define i32 @foo(i32 %a, i32 %b) {
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entry:
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%0 = mul i32 %a, %b
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%1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b)
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%2 = extractvalue { i32, i1 } %1, 0
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ret i32 %2
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}
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