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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101824 91177308-0d34-0410-b5e6-96231b3b80d8
215 lines
7.3 KiB
C++
215 lines
7.3 KiB
C++
//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the SPARC target.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcTargetMachine.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class SparcDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const SparcSubtarget &Subtarget;
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SparcTargetMachine& TM;
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public:
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explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
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: SelectionDAGISel(tm),
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Subtarget(tm.getSubtarget<SparcSubtarget>()),
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TM(tm) {
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}
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SDNode *Select(SDNode *N);
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDNode *Op, SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDNode *Op, SDValue N, SDValue &Base,
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SDValue &Offset);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps);
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virtual const char *getPassName() const {
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return "SPARC DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "SparcGenDAGISel.inc"
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private:
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SDNode* getGlobalBaseReg();
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};
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} // end anonymous namespace
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SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
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}
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bool SparcDAGToDAGISel::SelectADDRri(SDNode *Op, SDValue Addr,
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SDValue &Base, SDValue &Offset) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_simm13(CN)) {
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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// Constant offset from frame ref.
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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} else {
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Base = Addr.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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return true;
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}
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}
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
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Base = Addr.getOperand(1);
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool SparcDAGToDAGISel::SelectADDRrr(SDNode *Op, SDValue Addr,
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SDValue &R1, SDValue &R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).getNode()))
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return false; // Let the reg+imm pattern catch this!
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
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Addr.getOperand(1).getOpcode() == SPISD::Lo)
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return false; // Let the reg+imm pattern catch this!
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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return true;
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}
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R1 = Addr;
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R2 = CurDAG->getRegister(SP::G0, MVT::i32);
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return true;
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}
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SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
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DebugLoc dl = N->getDebugLoc();
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if (N->isMachineOpcode())
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return NULL; // Already selected.
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switch (N->getOpcode()) {
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default: break;
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case SPISD::GLOBAL_BASE_REG:
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return getGlobalBaseReg();
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case ISD::SDIV:
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case ISD::UDIV: {
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// FIXME: should use a custom expander to expose the SRA to the dag.
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SDValue DivLHS = N->getOperand(0);
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SDValue DivRHS = N->getOperand(1);
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// Set the Y register to the high-part.
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SDValue TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
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CurDAG->getTargetConstant(31, MVT::i32)), 0);
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} else {
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TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
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}
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TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Flag, TopPart,
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CurDAG->getRegister(SP::G0, MVT::i32)), 0);
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
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TopPart);
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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// FIXME: Handle mul by immediate.
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SDValue MulLHS = N->getOperand(0);
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SDValue MulRHS = N->getOperand(1);
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unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
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SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
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MulLHS, MulRHS);
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// The high part is in the Y register.
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return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
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return NULL;
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}
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}
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return SelectCode(N);
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool
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SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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if (!SelectADDRrr(Op.getNode(), Op, Op0, Op1))
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SelectADDRri(Op.getNode(), Op, Op0, Op1);
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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/// createSparcISelDag - This pass converts a legalized DAG into a
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/// SPARC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
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return new SparcDAGToDAGISel(TM);
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}
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