mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106279 91177308-0d34-0410-b5e6-96231b3b80d8
1107 lines
42 KiB
C++
1107 lines
42 KiB
C++
//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the interfaces that Sparc uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcISelLowering.h"
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#include "SparcTargetMachine.h"
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#include "SparcMachineFunctionInfo.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "SparcGenCallingConv.inc"
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SDValue
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SparcTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG) const {
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// CCValAssign - represent the assignment of the return value to locations.
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SmallVector<CCValAssign, 16> RVLocs;
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
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RVLocs, *DAG.getContext());
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// Analize return values.
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CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
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// If this is the first return lowered for this function, add the regs to the
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// liveout set for the function.
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if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
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for (unsigned i = 0; i != RVLocs.size(); ++i)
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if (RVLocs[i].isRegLoc())
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DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
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}
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SDValue Flag;
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
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Outs[i].Val, Flag);
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// Guarantee that all emitted copies are stuck together with flags.
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Flag = Chain.getValue(1);
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}
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if (Flag.getNode())
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return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
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return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain);
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}
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/// LowerFormalArguments - V8 uses a very simple ABI, where all values are
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/// passed in either one or two GPRs, including FP values. TODO: we should
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/// pass FP values in FP registers for fastcc functions.
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SDValue
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SparcTargetLowering::LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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&Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals)
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const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
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static const unsigned ArgRegs[] = {
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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};
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const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
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unsigned ArgOffset = 68;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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SDValue ArgValue;
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CCValAssign &VA = ArgLocs[i];
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// FIXME: We ignore the register assignments of AnalyzeFormalArguments
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// because it doesn't know how to split a double into two i32 registers.
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EVT ObjectVT = VA.getValVT();
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switch (ObjectVT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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if (!Ins[i].Used) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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InVals.push_back(DAG.getUNDEF(ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
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SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = ISD::AssertSext;
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Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
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DAG.getValueType(ObjectVT));
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Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
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}
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InVals.push_back(Arg);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
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true, false);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDValue Load;
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if (ObjectVT == MVT::i32) {
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Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
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false, false, 0);
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} else {
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ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
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// Sparc is big endian, so add an offset based on the ObjectVT.
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unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
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FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
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DAG.getConstant(Offset, MVT::i32));
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Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
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NULL, 0, ObjectVT, false, false, 0);
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Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
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}
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InVals.push_back(Load);
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}
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ArgOffset += 4;
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break;
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case MVT::f32:
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if (!Ins[i].Used) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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InVals.push_back(DAG.getUNDEF(ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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// FP value is passed in an integer register.
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unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
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SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
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Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
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InVals.push_back(Arg);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
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true, false);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0,
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false, false, 0);
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InVals.push_back(Load);
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}
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ArgOffset += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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if (!Ins[i].Used) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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InVals.push_back(DAG.getUNDEF(ObjectVT));
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} else {
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SDValue HiVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
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HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
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true, false);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
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false, false, 0);
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}
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SDValue LoVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
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LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4,
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true, false);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
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false, false, 0);
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}
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// Compose the two halves together into an i64 unit.
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SDValue WholeValue =
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DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
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// If we want a double, do a bit convert.
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if (ObjectVT == MVT::f64)
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WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
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InVals.push_back(WholeValue);
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}
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ArgOffset += 8;
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break;
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}
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}
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// Store remaining ArgRegs to the stack if this is a varargs function.
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if (isVarArg) {
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// Remember the vararg offset for the va_start implementation.
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FuncInfo->setVarArgsFrameOffset(ArgOffset);
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std::vector<SDValue> OutChains;
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for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
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unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
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SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
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true, false);
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SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0,
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false, false, 0));
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ArgOffset += 4;
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}
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if (!OutChains.empty()) {
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OutChains.push_back(Chain);
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&OutChains[0], OutChains.size());
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}
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}
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return Chain;
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}
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SDValue
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SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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// Sparc target does not yet support tail call optimization.
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isTailCall = false;
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#if 0
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs);
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CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
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// Get the size of the outgoing arguments stack space requirement.
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unsigned ArgsSize = CCInfo.getNextStackOffset();
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// FIXME: We can't use this until f64 is known to take two GPRs.
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#else
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(void)CC_Sparc32;
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// Count the size of the outgoing arguments.
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unsigned ArgsSize = 0;
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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switch (Outs[i].Val.getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unknown value type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::f32:
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ArgsSize += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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ArgsSize += 8;
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break;
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}
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}
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if (ArgsSize > 4*6)
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ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
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else
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ArgsSize = 0;
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#endif
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// Keep stack frames 8-byte aligned.
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ArgsSize = (ArgsSize+7) & ~7;
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
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SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
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SmallVector<SDValue, 8> MemOpChains;
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#if 0
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = Outs[i].Val;
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at
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// RegsToPass vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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continue;
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}
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assert(VA.isMemLoc());
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// Create a store off the stack pointer for this argument.
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SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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// FIXME: VERIFY THAT 68 IS RIGHT.
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SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0,
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false, false, 0));
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}
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#else
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static const unsigned ArgRegs[] = {
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SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
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};
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unsigned ArgOffset = 68;
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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SDValue Val = Outs[i].Val;
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EVT ObjectVT = Val.getValueType();
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SDValue ValToStore(0, 0);
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unsigned ObjSize;
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switch (ObjectVT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unhandled argument type!");
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case MVT::i32:
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ObjSize = 4;
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if (RegsToPass.size() >= 6) {
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ValToStore = Val;
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} else {
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RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
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}
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break;
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case MVT::f32:
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ObjSize = 4;
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if (RegsToPass.size() >= 6) {
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ValToStore = Val;
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} else {
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// Convert this to a FP value in an int reg.
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Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
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RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
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}
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break;
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case MVT::f64: {
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ObjSize = 8;
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if (RegsToPass.size() >= 6) {
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ValToStore = Val; // Whole thing is passed in memory.
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break;
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}
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// Break into top and bottom parts by storing to the stack and loading
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// out the parts as integers. Top part goes in a reg.
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SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
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SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
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Val, StackPtr, NULL, 0,
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false, false, 0);
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// Sparc is big-endian, so the high part comes first.
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SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0,
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false, false, 0);
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// Increment the pointer to the other half.
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StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
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DAG.getIntPtrConstant(4));
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// Load the low part.
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SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0,
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false, false, 0);
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RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
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if (RegsToPass.size() >= 6) {
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ValToStore = Lo;
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ArgOffset += 4;
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ObjSize = 4;
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} else {
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RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
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}
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break;
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}
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case MVT::i64: {
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ObjSize = 8;
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if (RegsToPass.size() >= 6) {
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ValToStore = Val; // Whole thing is passed in memory.
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break;
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}
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// Split the value into top and bottom part. Top part goes in a reg.
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SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
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DAG.getConstant(1, MVT::i32));
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SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
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DAG.getConstant(0, MVT::i32));
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RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
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if (RegsToPass.size() >= 6) {
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ValToStore = Lo;
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ArgOffset += 4;
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ObjSize = 4;
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} else {
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RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
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}
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break;
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}
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}
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if (ValToStore.getNode()) {
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SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
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|
SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
|
|
PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
|
|
MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
|
|
PtrOff, NULL, 0,
|
|
false, false, 0));
|
|
}
|
|
ArgOffset += ObjSize;
|
|
}
|
|
#endif
|
|
|
|
// Emit all stores, make sure the occur before any copies into physregs.
|
|
if (!MemOpChains.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
&MemOpChains[0], MemOpChains.size());
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token
|
|
// chain and flag operands which copy the outgoing args into registers.
|
|
// The InFlag in necessary since all emited instructions must be
|
|
// stuck together.
|
|
SDValue InFlag;
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
unsigned Reg = RegsToPass[i].first;
|
|
// Remap I0->I7 -> O0->O7.
|
|
if (Reg >= SP::I0 && Reg <= SP::I7)
|
|
Reg = Reg-SP::I0+SP::O0;
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
|
// Likewise ExternalSymbol -> TargetExternalSymbol.
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
|
|
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
|
|
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
|
|
|
|
std::vector<EVT> NodeTys;
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
SDValue Ops[] = { Chain, Callee, InFlag };
|
|
Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
|
|
DAG.getIntPtrConstant(0, true), InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// Assign locations to each value returned by this call.
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
CCState RVInfo(CallConv, isVarArg, DAG.getTarget(),
|
|
RVLocs, *DAG.getContext());
|
|
|
|
RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
unsigned Reg = RVLocs[i].getLocReg();
|
|
|
|
// Remap I0->I7 -> O0->O7.
|
|
if (Reg >= SP::I0 && Reg <= SP::I7)
|
|
Reg = Reg-SP::I0+SP::O0;
|
|
|
|
Chain = DAG.getCopyFromReg(Chain, dl, Reg,
|
|
RVLocs[i].getValVT(), InFlag).getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
InVals.push_back(Chain.getValue(0));
|
|
}
|
|
|
|
return Chain;
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// TargetLowering Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
|
|
/// condition.
|
|
static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
|
|
switch (CC) {
|
|
default: llvm_unreachable("Unknown integer condition code!");
|
|
case ISD::SETEQ: return SPCC::ICC_E;
|
|
case ISD::SETNE: return SPCC::ICC_NE;
|
|
case ISD::SETLT: return SPCC::ICC_L;
|
|
case ISD::SETGT: return SPCC::ICC_G;
|
|
case ISD::SETLE: return SPCC::ICC_LE;
|
|
case ISD::SETGE: return SPCC::ICC_GE;
|
|
case ISD::SETULT: return SPCC::ICC_CS;
|
|
case ISD::SETULE: return SPCC::ICC_LEU;
|
|
case ISD::SETUGT: return SPCC::ICC_GU;
|
|
case ISD::SETUGE: return SPCC::ICC_CC;
|
|
}
|
|
}
|
|
|
|
/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
|
|
/// FCC condition.
|
|
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
|
|
switch (CC) {
|
|
default: llvm_unreachable("Unknown fp condition code!");
|
|
case ISD::SETEQ:
|
|
case ISD::SETOEQ: return SPCC::FCC_E;
|
|
case ISD::SETNE:
|
|
case ISD::SETUNE: return SPCC::FCC_NE;
|
|
case ISD::SETLT:
|
|
case ISD::SETOLT: return SPCC::FCC_L;
|
|
case ISD::SETGT:
|
|
case ISD::SETOGT: return SPCC::FCC_G;
|
|
case ISD::SETLE:
|
|
case ISD::SETOLE: return SPCC::FCC_LE;
|
|
case ISD::SETGE:
|
|
case ISD::SETOGE: return SPCC::FCC_GE;
|
|
case ISD::SETULT: return SPCC::FCC_UL;
|
|
case ISD::SETULE: return SPCC::FCC_ULE;
|
|
case ISD::SETUGT: return SPCC::FCC_UG;
|
|
case ISD::SETUGE: return SPCC::FCC_UGE;
|
|
case ISD::SETUO: return SPCC::FCC_U;
|
|
case ISD::SETO: return SPCC::FCC_O;
|
|
case ISD::SETONE: return SPCC::FCC_LG;
|
|
case ISD::SETUEQ: return SPCC::FCC_UE;
|
|
}
|
|
}
|
|
|
|
SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
|
|
: TargetLowering(TM, new TargetLoweringObjectFileELF()) {
|
|
|
|
// Set up the register classes.
|
|
addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
|
|
addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
|
|
addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
|
|
|
|
// Turn FP extload into load/fextend
|
|
setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
|
|
// Sparc doesn't have i1 sign extending load
|
|
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
|
|
// Turn FP truncstore into trunc + store.
|
|
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
|
|
|
|
// Custom legalize GlobalAddress nodes into LO/HI parts.
|
|
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
|
|
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
|
|
setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
|
|
|
|
// Sparc doesn't have sext_inreg, replace them with shl/sra
|
|
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
|
|
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
|
|
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
|
|
|
|
// Sparc has no REM or DIVREM operations.
|
|
setOperationAction(ISD::UREM, MVT::i32, Expand);
|
|
setOperationAction(ISD::SREM, MVT::i32, Expand);
|
|
setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
|
|
setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
|
|
|
|
// Custom expand fp<->sint
|
|
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
|
|
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
|
|
|
|
// Expand fp<->uint
|
|
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
|
|
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
|
|
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
|
|
|
|
// Sparc has no select or setcc: expand to SELECT_CC.
|
|
setOperationAction(ISD::SELECT, MVT::i32, Expand);
|
|
setOperationAction(ISD::SELECT, MVT::f32, Expand);
|
|
setOperationAction(ISD::SELECT, MVT::f64, Expand);
|
|
setOperationAction(ISD::SETCC, MVT::i32, Expand);
|
|
setOperationAction(ISD::SETCC, MVT::f32, Expand);
|
|
setOperationAction(ISD::SETCC, MVT::f64, Expand);
|
|
|
|
// Sparc doesn't have BRCOND either, it has BR_CC.
|
|
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
|
|
setOperationAction(ISD::BRIND, MVT::Other, Expand);
|
|
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
|
|
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
|
|
setOperationAction(ISD::BR_CC, MVT::f32, Custom);
|
|
setOperationAction(ISD::BR_CC, MVT::f64, Custom);
|
|
|
|
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
|
|
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
|
|
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
|
|
|
|
// SPARC has no intrinsics for these particular operations.
|
|
setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
|
|
|
|
setOperationAction(ISD::FSIN , MVT::f64, Expand);
|
|
setOperationAction(ISD::FCOS , MVT::f64, Expand);
|
|
setOperationAction(ISD::FREM , MVT::f64, Expand);
|
|
setOperationAction(ISD::FSIN , MVT::f32, Expand);
|
|
setOperationAction(ISD::FCOS , MVT::f32, Expand);
|
|
setOperationAction(ISD::FREM , MVT::f32, Expand);
|
|
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
|
|
setOperationAction(ISD::CTTZ , MVT::i32, Expand);
|
|
setOperationAction(ISD::CTLZ , MVT::i32, Expand);
|
|
setOperationAction(ISD::ROTL , MVT::i32, Expand);
|
|
setOperationAction(ISD::ROTR , MVT::i32, Expand);
|
|
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
|
|
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
|
|
setOperationAction(ISD::FPOW , MVT::f64, Expand);
|
|
setOperationAction(ISD::FPOW , MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
|
|
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
|
|
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
|
|
|
|
// FIXME: Sparc provides these multiplies, but we don't have them yet.
|
|
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
|
|
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
|
|
|
|
// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
|
|
setOperationAction(ISD::VASTART , MVT::Other, Custom);
|
|
// VAARG needs to be lowered to not do unaligned accesses for doubles.
|
|
setOperationAction(ISD::VAARG , MVT::Other, Custom);
|
|
|
|
// Use the default implementation.
|
|
setOperationAction(ISD::VACOPY , MVT::Other, Expand);
|
|
setOperationAction(ISD::VAEND , MVT::Other, Expand);
|
|
setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
|
|
setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
|
|
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
|
|
|
|
// No debug info support yet.
|
|
setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
|
|
|
|
setStackPointerRegisterToSaveRestore(SP::O6);
|
|
|
|
if (TM.getSubtarget<SparcSubtarget>().isV9())
|
|
setOperationAction(ISD::CTPOP, MVT::i32, Legal);
|
|
|
|
computeRegisterProperties();
|
|
}
|
|
|
|
const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch (Opcode) {
|
|
default: return 0;
|
|
case SPISD::CMPICC: return "SPISD::CMPICC";
|
|
case SPISD::CMPFCC: return "SPISD::CMPFCC";
|
|
case SPISD::BRICC: return "SPISD::BRICC";
|
|
case SPISD::BRFCC: return "SPISD::BRFCC";
|
|
case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
|
|
case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
|
|
case SPISD::Hi: return "SPISD::Hi";
|
|
case SPISD::Lo: return "SPISD::Lo";
|
|
case SPISD::FTOI: return "SPISD::FTOI";
|
|
case SPISD::ITOF: return "SPISD::ITOF";
|
|
case SPISD::CALL: return "SPISD::CALL";
|
|
case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
|
|
}
|
|
}
|
|
|
|
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
|
|
/// be zero. Op is expected to be a target specific node. Used by DAG
|
|
/// combiner.
|
|
void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
|
|
const APInt &Mask,
|
|
APInt &KnownZero,
|
|
APInt &KnownOne,
|
|
const SelectionDAG &DAG,
|
|
unsigned Depth) const {
|
|
APInt KnownZero2, KnownOne2;
|
|
KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
|
|
|
|
switch (Op.getOpcode()) {
|
|
default: break;
|
|
case SPISD::SELECT_ICC:
|
|
case SPISD::SELECT_FCC:
|
|
DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
|
|
Depth+1);
|
|
DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
|
|
Depth+1);
|
|
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
|
|
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
|
|
|
|
// Only known if known in both the LHS and RHS.
|
|
KnownOne &= KnownOne2;
|
|
KnownZero &= KnownZero2;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
|
|
// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
|
|
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
|
|
ISD::CondCode CC, unsigned &SPCC) {
|
|
if (isa<ConstantSDNode>(RHS) &&
|
|
cast<ConstantSDNode>(RHS)->isNullValue() &&
|
|
CC == ISD::SETNE &&
|
|
((LHS.getOpcode() == SPISD::SELECT_ICC &&
|
|
LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
|
|
(LHS.getOpcode() == SPISD::SELECT_FCC &&
|
|
LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
|
|
isa<ConstantSDNode>(LHS.getOperand(0)) &&
|
|
isa<ConstantSDNode>(LHS.getOperand(1)) &&
|
|
cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
|
|
cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
|
|
SDValue CMPCC = LHS.getOperand(3);
|
|
SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
|
|
LHS = CMPCC.getOperand(0);
|
|
RHS = CMPCC.getOperand(1);
|
|
}
|
|
}
|
|
|
|
SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
|
// FIXME there isn't really any debug info here
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
|
|
SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
|
|
SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
|
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
|
|
|
|
SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
|
|
getPointerTy());
|
|
SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
|
|
SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
|
|
GlobalBase, RelAddr);
|
|
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
|
|
AbsAddr, NULL, 0, false, false, 0);
|
|
}
|
|
|
|
SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
|
|
// FIXME there isn't really any debug info here
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
const Constant *C = N->getConstVal();
|
|
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
|
|
SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
|
|
SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
|
|
|
|
SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
|
|
getPointerTy());
|
|
SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
|
|
SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
|
|
GlobalBase, RelAddr);
|
|
return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
|
|
AbsAddr, NULL, 0, false, false, 0);
|
|
}
|
|
|
|
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
// Convert the fp value to integer in an FP register.
|
|
assert(Op.getValueType() == MVT::i32);
|
|
Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
|
|
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
|
|
}
|
|
|
|
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
assert(Op.getOperand(0).getValueType() == MVT::i32);
|
|
SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
|
|
// Convert the int value to FP in an FP register.
|
|
return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
|
|
}
|
|
|
|
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue Chain = Op.getOperand(0);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
|
|
SDValue LHS = Op.getOperand(2);
|
|
SDValue RHS = Op.getOperand(3);
|
|
SDValue Dest = Op.getOperand(4);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
unsigned Opc, SPCC = ~0U;
|
|
|
|
// If this is a br_cc of a "setcc", and if the setcc got lowered into
|
|
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
|
|
LookThroughSetCC(LHS, RHS, CC, SPCC);
|
|
|
|
// Get the condition flag.
|
|
SDValue CompareFlag;
|
|
if (LHS.getValueType() == MVT::i32) {
|
|
std::vector<EVT> VTs;
|
|
VTs.push_back(MVT::i32);
|
|
VTs.push_back(MVT::Flag);
|
|
SDValue Ops[2] = { LHS, RHS };
|
|
CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
|
|
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
|
|
Opc = SPISD::BRICC;
|
|
} else {
|
|
CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
|
|
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
|
|
Opc = SPISD::BRFCC;
|
|
}
|
|
return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
|
|
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
|
|
}
|
|
|
|
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
SDValue TrueVal = Op.getOperand(2);
|
|
SDValue FalseVal = Op.getOperand(3);
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
unsigned Opc, SPCC = ~0U;
|
|
|
|
// If this is a select_cc of a "setcc", and if the setcc got lowered into
|
|
// an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
|
|
LookThroughSetCC(LHS, RHS, CC, SPCC);
|
|
|
|
SDValue CompareFlag;
|
|
if (LHS.getValueType() == MVT::i32) {
|
|
std::vector<EVT> VTs;
|
|
VTs.push_back(LHS.getValueType()); // subcc returns a value
|
|
VTs.push_back(MVT::Flag);
|
|
SDValue Ops[2] = { LHS, RHS };
|
|
CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
|
|
Opc = SPISD::SELECT_ICC;
|
|
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
|
|
} else {
|
|
CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
|
|
Opc = SPISD::SELECT_FCC;
|
|
if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
|
|
}
|
|
return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
|
|
DAG.getConstant(SPCC, MVT::i32), CompareFlag);
|
|
}
|
|
|
|
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
|
|
const SparcTargetLowering &TLI) {
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
|
|
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
// memory location argument.
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
SDValue Offset =
|
|
DAG.getNode(ISD::ADD, dl, MVT::i32,
|
|
DAG.getRegister(SP::I6, MVT::i32),
|
|
DAG.getConstant(FuncInfo->getVarArgsFrameOffset(),
|
|
MVT::i32));
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0,
|
|
false, false, 0);
|
|
}
|
|
|
|
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
|
|
SDNode *Node = Op.getNode();
|
|
EVT VT = Node->getValueType(0);
|
|
SDValue InChain = Node->getOperand(0);
|
|
SDValue VAListPtr = Node->getOperand(1);
|
|
const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
|
|
DebugLoc dl = Node->getDebugLoc();
|
|
SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0,
|
|
false, false, 0);
|
|
// Increment the pointer, VAList, to the next vaarg
|
|
SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
|
|
DAG.getConstant(VT.getSizeInBits()/8,
|
|
MVT::i32));
|
|
// Store the incremented VAList to the legalized pointer
|
|
InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
|
|
VAListPtr, SV, 0, false, false, 0);
|
|
// Load the actual argument out of the pointer VAList, unless this is an
|
|
// f64 load.
|
|
if (VT != MVT::f64)
|
|
return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0, false, false, 0);
|
|
|
|
// Otherwise, load it as i64, then do a bitconvert.
|
|
SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0,
|
|
false, false, 0);
|
|
|
|
// Bit-Convert the value to f64.
|
|
SDValue Ops[2] = {
|
|
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
|
|
V.getValue(1)
|
|
};
|
|
return DAG.getMergeValues(Ops, 2, dl);
|
|
}
|
|
|
|
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
|
|
SDValue Chain = Op.getOperand(0); // Legalize the chain.
|
|
SDValue Size = Op.getOperand(1); // Legalize the size.
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
unsigned SPReg = SP::O6;
|
|
SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
|
|
SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
|
|
Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
|
|
|
|
// The resultant pointer is actually 16 words from the bottom of the stack,
|
|
// to provide a register spill area.
|
|
SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
|
|
DAG.getConstant(96, MVT::i32));
|
|
SDValue Ops[2] = { NewVal, Chain };
|
|
return DAG.getMergeValues(Ops, 2, dl);
|
|
}
|
|
|
|
|
|
SDValue SparcTargetLowering::
|
|
LowerOperation(SDValue Op, SelectionDAG &DAG) const {
|
|
switch (Op.getOpcode()) {
|
|
default: llvm_unreachable("Should not custom lower this!");
|
|
// Frame & Return address. Currently unimplemented
|
|
case ISD::RETURNADDR: return SDValue();
|
|
case ISD::FRAMEADDR: return SDValue();
|
|
case ISD::GlobalTLSAddress:
|
|
llvm_unreachable("TLS not implemented for Sparc.");
|
|
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
|
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
|
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
|
|
case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
|
|
case ISD::BR_CC: return LowerBR_CC(Op, DAG);
|
|
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
|
|
case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
|
|
case ISD::VAARG: return LowerVAARG(Op, DAG);
|
|
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
|
|
}
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *BB) const {
|
|
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
|
|
unsigned BROpcode;
|
|
unsigned CC;
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
// Figure out the conditional branch opcode to use for this select_cc.
|
|
switch (MI->getOpcode()) {
|
|
default: llvm_unreachable("Unknown SELECT_CC!");
|
|
case SP::SELECT_CC_Int_ICC:
|
|
case SP::SELECT_CC_FP_ICC:
|
|
case SP::SELECT_CC_DFP_ICC:
|
|
BROpcode = SP::BCOND;
|
|
break;
|
|
case SP::SELECT_CC_Int_FCC:
|
|
case SP::SELECT_CC_FP_FCC:
|
|
case SP::SELECT_CC_DFP_FCC:
|
|
BROpcode = SP::FBCOND;
|
|
break;
|
|
}
|
|
|
|
CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
|
|
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
|
|
// control-flow pattern. The incoming instruction knows the destination vreg
|
|
// to set, the condition code register to branch on, the true/false values to
|
|
// select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator It = BB;
|
|
++It;
|
|
|
|
// thisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// [f]bCC copy1MBB
|
|
// fallthrough --> copy0MBB
|
|
MachineBasicBlock *thisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
|
|
F->insert(It, copy0MBB);
|
|
F->insert(It, sinkMBB);
|
|
// Update machine-CFG edges by first adding all successors of the current
|
|
// block to the new block which will contain the Phi node for the select.
|
|
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
|
|
E = BB->succ_end(); I != E; ++I)
|
|
sinkMBB->addSuccessor(*I);
|
|
// Next, remove all successors of the current block, and add the true
|
|
// and fallthrough blocks as its successors.
|
|
while (!BB->succ_empty())
|
|
BB->removeSuccessor(BB->succ_begin());
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(copy0MBB);
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to sinkMBB
|
|
BB = copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
// sinkMBB:
|
|
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
|
|
// ...
|
|
BB = sinkMBB;
|
|
BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
|
|
|
|
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Sparc Inline Assembly Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
/// constraint it is for this target.
|
|
SparcTargetLowering::ConstraintType
|
|
SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
default: break;
|
|
case 'r': return C_RegisterClass;
|
|
}
|
|
}
|
|
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
}
|
|
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
|
SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
|
|
EVT VT) const {
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
case 'r':
|
|
return std::make_pair(0U, SP::IntRegsRegisterClass);
|
|
}
|
|
}
|
|
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
}
|
|
|
|
std::vector<unsigned> SparcTargetLowering::
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
EVT VT) const {
|
|
if (Constraint.size() != 1)
|
|
return std::vector<unsigned>();
|
|
|
|
switch (Constraint[0]) {
|
|
default: break;
|
|
case 'r':
|
|
return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
|
|
SP::L4, SP::L5, SP::L6, SP::L7,
|
|
SP::I0, SP::I1, SP::I2, SP::I3,
|
|
SP::I4, SP::I5,
|
|
SP::O0, SP::O1, SP::O2, SP::O3,
|
|
SP::O4, SP::O5, SP::O7, 0);
|
|
}
|
|
|
|
return std::vector<unsigned>();
|
|
}
|
|
|
|
bool
|
|
SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
|
|
// The Sparc target isn't yet aware of offsets.
|
|
return false;
|
|
}
|
|
|
|
/// getFunctionAlignment - Return the Log2 alignment of this function.
|
|
unsigned SparcTargetLowering::getFunctionAlignment(const Function *) const {
|
|
return 2;
|
|
}
|