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subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198685 91177308-0d34-0410-b5e6-96231b3b80d8
247 lines
8.3 KiB
C++
247 lines
8.3 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsTargetMachine.h"
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#include "Mips.h"
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#include "Mips16FrameLowering.h"
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#include "Mips16HardFloat.h"
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#include "Mips16ISelDAGToDAG.h"
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#include "Mips16ISelLowering.h"
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#include "Mips16InstrInfo.h"
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#include "MipsFrameLowering.h"
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#include "MipsInstrInfo.h"
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#include "MipsModuleISelDAGToDAG.h"
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#include "MipsOs16.h"
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#include "MipsSEFrameLowering.h"
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#include "MipsSEISelDAGToDAG.h"
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#include "MipsSEISelLowering.h"
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#include "MipsSEInstrInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
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RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
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RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
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}
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static std::string computeDataLayout(const MipsSubtarget &ST) {
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std::string Ret = "";
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// There are both little and big endian mips.
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if (ST.isLittle())
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Ret += "e";
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else
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Ret += "E";
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Ret += "-m:m";
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// Pointers are 32 bit on some ABIs.
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if (!ST.isABI_N64())
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Ret += "-p:32:32";
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// 8 and 16 bit integers only need no have natural alignment, but try to
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// align them to 32 bits. 64 bit integers have natural alignment.
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Ret += "-i8:8:32-i16:16:32-i64:64";
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// 32 bit registers are always available and the stack is at least 64 bit
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// aligned. On N64 64 bit registers are also available and the stack is
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// 128 bit aligned.
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if (ST.isABI_N64() || ST.isABI_N32())
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Ret += "-n32:64-S128";
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else
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Ret += "-n32-S64";
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return Ret;
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}
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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// Using CodeModel::Large enables different CALL behavior.
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MipsTargetMachine::
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MipsTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool isLittle)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, isLittle, RM, this),
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DL(computeDataLayout(Subtarget)),
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InstrInfo(MipsInstrInfo::create(*this)),
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FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
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TLInfo(MipsTargetLowering::create(*this)), TSInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()), JITInfo() {
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initAsmInfo();
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}
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void MipsTargetMachine::setHelperClassesMips16() {
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InstrInfoSE.swap(InstrInfo);
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FrameLoweringSE.swap(FrameLowering);
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TLInfoSE.swap(TLInfo);
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if (!InstrInfo16) {
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InstrInfo.reset(MipsInstrInfo::create(*this));
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FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
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TLInfo.reset(MipsTargetLowering::create(*this));
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} else {
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InstrInfo16.swap(InstrInfo);
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FrameLowering16.swap(FrameLowering);
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TLInfo16.swap(TLInfo);
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}
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assert(TLInfo && "null target lowering 16");
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assert(InstrInfo && "null instr info 16");
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assert(FrameLowering && "null frame lowering 16");
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}
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void MipsTargetMachine::setHelperClassesMipsSE() {
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InstrInfo16.swap(InstrInfo);
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FrameLowering16.swap(FrameLowering);
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TLInfo16.swap(TLInfo);
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if (!InstrInfoSE) {
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InstrInfo.reset(MipsInstrInfo::create(*this));
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FrameLowering.reset(MipsFrameLowering::create(*this, Subtarget));
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TLInfo.reset(MipsTargetLowering::create(*this));
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} else {
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InstrInfoSE.swap(InstrInfo);
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FrameLoweringSE.swap(FrameLowering);
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TLInfoSE.swap(TLInfo);
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}
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assert(TLInfo && "null target lowering in SE");
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assert(InstrInfo && "null instr info SE");
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assert(FrameLowering && "null frame lowering SE");
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}
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void MipsebTargetMachine::anchor() { }
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MipsebTargetMachine::
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MipsebTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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void MipselTargetMachine::anchor() { }
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MipselTargetMachine::
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MipselTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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namespace {
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/// Mips Code Generator Pass Configuration Options.
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class MipsPassConfig : public TargetPassConfig {
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public:
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MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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// The current implementation of long branch pass requires a scratch
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// register ($at) to be available before branch instructions. Tail merging
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// can break this requirement, so disable it when long branch pass is
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// enabled.
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EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
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}
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MipsTargetMachine &getMipsTargetMachine() const {
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return getTM<MipsTargetMachine>();
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}
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const MipsSubtarget &getMipsSubtarget() const {
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return *getMipsTargetMachine().getSubtargetImpl();
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}
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virtual void addIRPasses();
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virtual bool addInstSelector();
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virtual void addMachineSSAOptimization();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new MipsPassConfig(this, PM);
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}
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void MipsPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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if (getMipsSubtarget().os16())
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addPass(createMipsOs16(getMipsTargetMachine()));
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if (getMipsSubtarget().inMips16HardFloat())
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addPass(createMips16HardFloat(getMipsTargetMachine()));
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addPass(createPartiallyInlineLibCallsPass());
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}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsPassConfig::addInstSelector() {
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if (getMipsSubtarget().allowMixed16_32()) {
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addPass(createMipsModuleISelDag(getMipsTargetMachine()));
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addPass(createMips16ISelDag(getMipsTargetMachine()));
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addPass(createMipsSEISelDag(getMipsTargetMachine()));
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} else {
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addPass(createMipsISelDag(getMipsTargetMachine()));
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}
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return false;
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}
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void MipsPassConfig::addMachineSSAOptimization() {
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addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
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TargetPassConfig::addMachineSSAOptimization();
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}
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void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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if (Subtarget.allowMixed16_32()) {
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DEBUG(errs() << "No ");
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//FIXME: The Basic Target Transform Info
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// pass needs to become a function pass instead of
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// being an immutable pass and then this method as it exists now
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// would be unnecessary.
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PM.add(createNoTargetTransformInfoPass());
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} else
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LLVMTargetMachine::addAnalysisPasses(PM);
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DEBUG(errs() << "Target Transform Info Pass Added\n");
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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bool MipsPassConfig::addPreEmitPass() {
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MipsTargetMachine &TM = getMipsTargetMachine();
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const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
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addPass(createMipsDelaySlotFillerPass(TM));
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if (Subtarget.enableLongBranchPass())
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addPass(createMipsLongBranchPass(TM));
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if (Subtarget.inMips16Mode() ||
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Subtarget.allowMixed16_32())
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addPass(createMipsConstantIslandPass(TM));
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return true;
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}
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bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for Mips.
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PM.add(createMipsJITCodeEmitterPass(*this, JCE));
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return false;
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}
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