Bill Wendling e9a7286087 Use "SINT_TO_FP" instead of "UINT_TO_FP" when getting the exponent. This was ... causing the limited precision stuff to produce the wrong result for values in the range [0, 1). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62615 91177308-0d34-0410-b5e6-96231b3b80d8		2009-01-20 21:17:57 +00:00
..
CallingConvLower.cpp
CMakeLists.txt
DAGCombiner.cpp	Fix a dagcombine to not generate loads of non-round integer types,	2009-01-20 01:06:45 +00:00
FastISel.cpp	Verify debug info.	2009-01-19 23:21:49 +00:00
LegalizeDAG.cpp
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp	Few targets like PIC16 wants libcall generation for illegal type i16.	2009-01-18 18:25:27 +00:00
LegalizeTypes.cpp
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp	Initial hazard recognizer support in post-pass scheduling. This includes	2009-01-16 01:33:36 +00:00
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp	CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.	2009-01-16 20:57:18 +00:00
ScheduleDAGSDNodesEmit.cpp	Instead of adding dependence edges between terminator instructions	2009-01-16 22:10:20 +00:00
SelectionDAG.cpp	Remove SDNode's virtual destructor. This makes it impossible for	2009-01-19 22:39:36 +00:00
SelectionDAGBuild.cpp	Use "SINT_TO_FP" instead of "UINT_TO_FP" when getting the exponent. This was	2009-01-20 21:17:57 +00:00
SelectionDAGBuild.h
SelectionDAGISel.cpp	Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.	2009-01-20 19:12:24 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Few targets like PIC16 wants libcall generation for illegal type i16.	2009-01-18 18:25:27 +00:00