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SelectionDAGBuilder::removeValue is dead now, after rL236563. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236618 91177308-0d34-0410-b5e6-96231b3b80d8
954 lines
38 KiB
C++
954 lines
38 KiB
C++
//===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements routines for translating from LLVM IR into SelectionDAG IR.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
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#define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
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#include "StatepointLowering.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/IR/CallSite.h"
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#include "llvm/IR/Statepoint.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetLowering.h"
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#include <vector>
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namespace llvm {
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class AddrSpaceCastInst;
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class AliasAnalysis;
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class AllocaInst;
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class BasicBlock;
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class BitCastInst;
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class BranchInst;
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class CallInst;
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class DbgValueInst;
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class ExtractElementInst;
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class ExtractValueInst;
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class FCmpInst;
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class FPExtInst;
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class FPToSIInst;
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class FPToUIInst;
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class FPTruncInst;
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class Function;
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class FunctionLoweringInfo;
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class GetElementPtrInst;
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class GCFunctionInfo;
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class ICmpInst;
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class IntToPtrInst;
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class IndirectBrInst;
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class InvokeInst;
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class InsertElementInst;
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class InsertValueInst;
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class Instruction;
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class LoadInst;
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class MachineBasicBlock;
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class MachineInstr;
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class MachineRegisterInfo;
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class MDNode;
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class MVT;
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class PHINode;
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class PtrToIntInst;
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class ReturnInst;
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class SDDbgValue;
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class SExtInst;
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class SelectInst;
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class ShuffleVectorInst;
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class SIToFPInst;
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class StoreInst;
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class SwitchInst;
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class DataLayout;
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class TargetLibraryInfo;
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class TargetLowering;
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class TruncInst;
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class UIToFPInst;
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class UnreachableInst;
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class VAArgInst;
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class ZExtInst;
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//===----------------------------------------------------------------------===//
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/// SelectionDAGBuilder - This is the common target-independent lowering
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/// implementation that is parameterized by a TargetLowering object.
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///
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class SelectionDAGBuilder {
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/// CurInst - The current instruction being visited
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const Instruction *CurInst;
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DenseMap<const Value*, SDValue> NodeMap;
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/// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
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/// to preserve debug information for incoming arguments.
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DenseMap<const Value*, SDValue> UnusedArgNodeMap;
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/// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
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class DanglingDebugInfo {
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const DbgValueInst* DI;
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DebugLoc dl;
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unsigned SDNodeOrder;
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public:
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DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
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DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
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DI(di), dl(DL), SDNodeOrder(SDNO) { }
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const DbgValueInst* getDI() { return DI; }
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DebugLoc getdl() { return dl; }
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unsigned getSDNodeOrder() { return SDNodeOrder; }
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};
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/// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
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/// yet seen the referent. We defer handling these until we do see it.
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DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
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public:
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/// PendingLoads - Loads are not emitted to the program immediately. We bunch
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/// them up and then emit token factor nodes when possible. This allows us to
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/// get simple disambiguation between loads without worrying about alias
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/// analysis.
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SmallVector<SDValue, 8> PendingLoads;
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/// State used while lowering a statepoint sequence (gc_statepoint,
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/// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
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StatepointLoweringState StatepointLowering;
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private:
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/// PendingExports - CopyToReg nodes that copy values to virtual registers
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/// for export to other blocks need to be emitted before any terminator
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/// instruction, but they have no other ordering requirements. We bunch them
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/// up and the emit a single tokenfactor for them just before terminator
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/// instructions.
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SmallVector<SDValue, 8> PendingExports;
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/// SDNodeOrder - A unique monotonically increasing number used to order the
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/// SDNodes we create.
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unsigned SDNodeOrder;
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enum CaseClusterKind {
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/// A cluster of adjacent case labels with the same destination, or just one
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/// case.
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CC_Range,
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/// A cluster of cases suitable for jump table lowering.
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CC_JumpTable,
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/// A cluster of cases suitable for bit test lowering.
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CC_BitTests
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};
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/// A cluster of case labels.
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struct CaseCluster {
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CaseClusterKind Kind;
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const ConstantInt *Low, *High;
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union {
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MachineBasicBlock *MBB;
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unsigned JTCasesIndex;
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unsigned BTCasesIndex;
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};
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uint32_t Weight;
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static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
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MachineBasicBlock *MBB, uint32_t Weight) {
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CaseCluster C;
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C.Kind = CC_Range;
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C.Low = Low;
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C.High = High;
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C.MBB = MBB;
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C.Weight = Weight;
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return C;
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}
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static CaseCluster jumpTable(const ConstantInt *Low,
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const ConstantInt *High, unsigned JTCasesIndex,
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uint32_t Weight) {
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CaseCluster C;
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C.Kind = CC_JumpTable;
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C.Low = Low;
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C.High = High;
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C.JTCasesIndex = JTCasesIndex;
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C.Weight = Weight;
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return C;
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}
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static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
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unsigned BTCasesIndex, uint32_t Weight) {
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CaseCluster C;
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C.Kind = CC_BitTests;
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C.Low = Low;
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C.High = High;
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C.BTCasesIndex = BTCasesIndex;
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C.Weight = Weight;
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return C;
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}
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};
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typedef std::vector<CaseCluster> CaseClusterVector;
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typedef CaseClusterVector::iterator CaseClusterIt;
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struct CaseBits {
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uint64_t Mask;
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MachineBasicBlock* BB;
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unsigned Bits;
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uint32_t ExtraWeight;
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CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
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uint32_t Weight):
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Mask(mask), BB(bb), Bits(bits), ExtraWeight(Weight) { }
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CaseBits() : Mask(0), BB(nullptr), Bits(0), ExtraWeight(0) {}
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};
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typedef std::vector<CaseBits> CaseBitsVector;
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/// Sort Clusters and merge adjacent cases.
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void sortAndRangeify(CaseClusterVector &Clusters);
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/// CaseBlock - This structure is used to communicate between
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/// SelectionDAGBuilder and SDISel for the code generation of additional basic
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/// blocks needed by multi-case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
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const Value *cmpmiddle,
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me,
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uint32_t trueweight = 0, uint32_t falseweight = 0)
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
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TrueWeight(trueweight), FalseWeight(falseweight) { }
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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const Value *CmpLHS, *CmpMHS, *CmpRHS;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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// TrueWeight/FalseWeight - branch weights.
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uint32_t TrueWeight, FalseWeight;
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};
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struct JumpTable {
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
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MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
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/// Reg - the virtual register containing the index of the jump table entry
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//. to jump to.
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unsigned Reg;
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/// JTI - the JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// MBB - the MBB into which to emit the code for the indirect jump.
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MachineBasicBlock *MBB;
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/// Default - the MBB of the default bb, which is a successor of the range
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/// check MBB. This is when updating PHI nodes in successors.
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MachineBasicBlock *Default;
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};
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struct JumpTableHeader {
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JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
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bool E = false):
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First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
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APInt First;
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APInt Last;
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const Value *SValue;
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MachineBasicBlock *HeaderBB;
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bool Emitted;
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};
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typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
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struct BitTestCase {
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BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
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uint32_t Weight):
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Mask(M), ThisBB(T), TargetBB(Tr), ExtraWeight(Weight) { }
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uint64_t Mask;
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MachineBasicBlock *ThisBB;
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MachineBasicBlock *TargetBB;
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uint32_t ExtraWeight;
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};
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typedef SmallVector<BitTestCase, 3> BitTestInfo;
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struct BitTestBlock {
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BitTestBlock(APInt F, APInt R, const Value* SV,
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unsigned Rg, MVT RgVT, bool E,
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MachineBasicBlock* P, MachineBasicBlock* D,
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BitTestInfo C):
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First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
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Parent(P), Default(D), Cases(std::move(C)) { }
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APInt First;
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APInt Range;
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const Value *SValue;
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unsigned Reg;
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MVT RegVT;
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bool Emitted;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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BitTestInfo Cases;
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};
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/// Minimum jump table density, in percent.
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enum { MinJumpTableDensity = 40 };
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/// Check whether a range of clusters is dense enough for a jump table.
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bool isDense(const CaseClusterVector &Clusters, unsigned *TotalCases,
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unsigned First, unsigned Last);
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/// Build a jump table cluster from Clusters[First..Last]. Returns false if it
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/// decides it's not a good idea.
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bool buildJumpTable(CaseClusterVector &Clusters, unsigned First,
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unsigned Last, const SwitchInst *SI,
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MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
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/// Find clusters of cases suitable for jump table lowering.
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void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
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MachineBasicBlock *DefaultMBB);
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/// Check whether the range [Low,High] fits in a machine word.
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bool rangeFitsInWord(const APInt &Low, const APInt &High);
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/// Check whether these clusters are suitable for lowering with bit tests based
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/// on the number of destinations, comparison metric, and range.
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bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
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const APInt &Low, const APInt &High);
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/// Build a bit test cluster from Clusters[First..Last]. Returns false if it
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/// decides it's not a good idea.
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bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
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const SwitchInst *SI, CaseCluster &BTCluster);
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/// Find clusters of cases suitable for bit test lowering.
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void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
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struct SwitchWorkListItem {
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MachineBasicBlock *MBB;
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CaseClusterIt FirstCluster;
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CaseClusterIt LastCluster;
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const ConstantInt *GE;
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const ConstantInt *LT;
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};
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typedef SmallVector<SwitchWorkListItem, 4> SwitchWorkList;
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/// Emit comparison and split W into two subtrees.
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void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
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Value *Cond, MachineBasicBlock *SwitchMBB);
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/// Lower W.
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void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
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MachineBasicBlock *SwitchMBB,
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MachineBasicBlock *DefaultMBB);
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/// A class which encapsulates all of the information needed to generate a
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/// stack protector check and signals to isel via its state being initialized
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/// that a stack protector needs to be generated.
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///
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/// *NOTE* The following is a high level documentation of SelectionDAG Stack
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/// Protector Generation. The reason that it is placed here is for a lack of
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/// other good places to stick it.
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///
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/// High Level Overview of SelectionDAG Stack Protector Generation:
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///
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/// Previously, generation of stack protectors was done exclusively in the
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/// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
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/// splitting basic blocks at the IR level to create the success/failure basic
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/// blocks in the tail of the basic block in question. As a result of this,
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/// calls that would have qualified for the sibling call optimization were no
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/// longer eligible for optimization since said calls were no longer right in
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/// the "tail position" (i.e. the immediate predecessor of a ReturnInst
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/// instruction).
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///
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/// Then it was noticed that since the sibling call optimization causes the
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/// callee to reuse the caller's stack, if we could delay the generation of
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/// the stack protector check until later in CodeGen after the sibling call
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/// decision was made, we get both the tail call optimization and the stack
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/// protector check!
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///
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/// A few goals in solving this problem were:
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///
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/// 1. Preserve the architecture independence of stack protector generation.
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///
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/// 2. Preserve the normal IR level stack protector check for platforms like
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/// OpenBSD for which we support platform-specific stack protector
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/// generation.
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///
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/// The main problem that guided the present solution is that one can not
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/// solve this problem in an architecture independent manner at the IR level
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/// only. This is because:
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///
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/// 1. The decision on whether or not to perform a sibling call on certain
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/// platforms (for instance i386) requires lower level information
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/// related to available registers that can not be known at the IR level.
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///
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/// 2. Even if the previous point were not true, the decision on whether to
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/// perform a tail call is done in LowerCallTo in SelectionDAG which
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/// occurs after the Stack Protector Pass. As a result, one would need to
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/// put the relevant callinst into the stack protector check success
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/// basic block (where the return inst is placed) and then move it back
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/// later at SelectionDAG/MI time before the stack protector check if the
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/// tail call optimization failed. The MI level option was nixed
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/// immediately since it would require platform-specific pattern
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/// matching. The SelectionDAG level option was nixed because
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/// SelectionDAG only processes one IR level basic block at a time
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/// implying one could not create a DAG Combine to move the callinst.
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///
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/// To get around this problem a few things were realized:
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///
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/// 1. While one can not handle multiple IR level basic blocks at the
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/// SelectionDAG Level, one can generate multiple machine basic blocks
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/// for one IR level basic block. This is how we handle bit tests and
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/// switches.
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///
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/// 2. At the MI level, tail calls are represented via a special return
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/// MIInst called "tcreturn". Thus if we know the basic block in which we
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/// wish to insert the stack protector check, we get the correct behavior
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/// by always inserting the stack protector check right before the return
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/// statement. This is a "magical transformation" since no matter where
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/// the stack protector check intrinsic is, we always insert the stack
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/// protector check code at the end of the BB.
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///
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/// Given the aforementioned constraints, the following solution was devised:
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///
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/// 1. On platforms that do not support SelectionDAG stack protector check
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/// generation, allow for the normal IR level stack protector check
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/// generation to continue.
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///
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/// 2. On platforms that do support SelectionDAG stack protector check
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/// generation:
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///
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/// a. Use the IR level stack protector pass to decide if a stack
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/// protector is required/which BB we insert the stack protector check
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/// in by reusing the logic already therein. If we wish to generate a
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/// stack protector check in a basic block, we place a special IR
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/// intrinsic called llvm.stackprotectorcheck right before the BB's
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/// returninst or if there is a callinst that could potentially be
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/// sibling call optimized, before the call inst.
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///
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/// b. Then when a BB with said intrinsic is processed, we codegen the BB
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/// normally via SelectBasicBlock. In said process, when we visit the
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/// stack protector check, we do not actually emit anything into the
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/// BB. Instead, we just initialize the stack protector descriptor
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/// class (which involves stashing information/creating the success
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/// mbbb and the failure mbb if we have not created one for this
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/// function yet) and export the guard variable that we are going to
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/// compare.
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///
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/// c. After we finish selecting the basic block, in FinishBasicBlock if
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/// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
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/// initialized, we first find a splice point in the parent basic block
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/// before the terminator and then splice the terminator of said basic
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/// block into the success basic block. Then we code-gen a new tail for
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/// the parent basic block consisting of the two loads, the comparison,
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/// and finally two branches to the success/failure basic blocks. We
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/// conclude by code-gening the failure basic block if we have not
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/// code-gened it already (all stack protector checks we generate in
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/// the same function, use the same failure basic block).
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class StackProtectorDescriptor {
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public:
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StackProtectorDescriptor() : ParentMBB(nullptr), SuccessMBB(nullptr),
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FailureMBB(nullptr), Guard(nullptr),
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GuardReg(0) { }
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/// Returns true if all fields of the stack protector descriptor are
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/// initialized implying that we should/are ready to emit a stack protector.
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bool shouldEmitStackProtector() const {
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return ParentMBB && SuccessMBB && FailureMBB && Guard;
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}
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/// Initialize the stack protector descriptor structure for a new basic
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/// block.
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void initialize(const BasicBlock *BB,
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MachineBasicBlock *MBB,
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const CallInst &StackProtCheckCall) {
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// Make sure we are not initialized yet.
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assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
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"already initialized!");
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ParentMBB = MBB;
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SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
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FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
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if (!Guard)
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Guard = StackProtCheckCall.getArgOperand(0);
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|
}
|
|
|
|
/// Reset state that changes when we handle different basic blocks.
|
|
///
|
|
/// This currently includes:
|
|
///
|
|
/// 1. The specific basic block we are generating a
|
|
/// stack protector for (ParentMBB).
|
|
///
|
|
/// 2. The successor machine basic block that will contain the tail of
|
|
/// parent mbb after we create the stack protector check (SuccessMBB). This
|
|
/// BB is visited only on stack protector check success.
|
|
void resetPerBBState() {
|
|
ParentMBB = nullptr;
|
|
SuccessMBB = nullptr;
|
|
}
|
|
|
|
/// Reset state that only changes when we switch functions.
|
|
///
|
|
/// This currently includes:
|
|
///
|
|
/// 1. FailureMBB since we reuse the failure code path for all stack
|
|
/// protector checks created in an individual function.
|
|
///
|
|
/// 2.The guard variable since the guard variable we are checking against is
|
|
/// always the same.
|
|
void resetPerFunctionState() {
|
|
FailureMBB = nullptr;
|
|
Guard = nullptr;
|
|
}
|
|
|
|
MachineBasicBlock *getParentMBB() { return ParentMBB; }
|
|
MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
|
|
MachineBasicBlock *getFailureMBB() { return FailureMBB; }
|
|
const Value *getGuard() { return Guard; }
|
|
|
|
unsigned getGuardReg() const { return GuardReg; }
|
|
void setGuardReg(unsigned R) { GuardReg = R; }
|
|
|
|
private:
|
|
/// The basic block for which we are generating the stack protector.
|
|
///
|
|
/// As a result of stack protector generation, we will splice the
|
|
/// terminators of this basic block into the successor mbb SuccessMBB and
|
|
/// replace it with a compare/branch to the successor mbbs
|
|
/// SuccessMBB/FailureMBB depending on whether or not the stack protector
|
|
/// was violated.
|
|
MachineBasicBlock *ParentMBB;
|
|
|
|
/// A basic block visited on stack protector check success that contains the
|
|
/// terminators of ParentMBB.
|
|
MachineBasicBlock *SuccessMBB;
|
|
|
|
/// This basic block visited on stack protector check failure that will
|
|
/// contain a call to __stack_chk_fail().
|
|
MachineBasicBlock *FailureMBB;
|
|
|
|
/// The guard variable which we will compare against the stored value in the
|
|
/// stack protector stack slot.
|
|
const Value *Guard;
|
|
|
|
/// The virtual register holding the stack guard value.
|
|
unsigned GuardReg;
|
|
|
|
/// Add a successor machine basic block to ParentMBB. If the successor mbb
|
|
/// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
|
|
/// block will be created. Assign a large weight if IsLikely is true.
|
|
MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
|
|
MachineBasicBlock *ParentMBB,
|
|
bool IsLikely,
|
|
MachineBasicBlock *SuccMBB = nullptr);
|
|
};
|
|
|
|
private:
|
|
const TargetMachine &TM;
|
|
public:
|
|
/// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
|
|
/// nodes without a corresponding SDNode.
|
|
static const unsigned LowestSDNodeOrder = 1;
|
|
|
|
SelectionDAG &DAG;
|
|
const DataLayout *DL;
|
|
AliasAnalysis *AA;
|
|
const TargetLibraryInfo *LibInfo;
|
|
|
|
/// SwitchCases - Vector of CaseBlock structures used to communicate
|
|
/// SwitchInst code generation information.
|
|
std::vector<CaseBlock> SwitchCases;
|
|
/// JTCases - Vector of JumpTable structures used to communicate
|
|
/// SwitchInst code generation information.
|
|
std::vector<JumpTableBlock> JTCases;
|
|
/// BitTestCases - Vector of BitTestBlock structures used to communicate
|
|
/// SwitchInst code generation information.
|
|
std::vector<BitTestBlock> BitTestCases;
|
|
/// A StackProtectorDescriptor structure used to communicate stack protector
|
|
/// information in between SelectBasicBlock and FinishBasicBlock.
|
|
StackProtectorDescriptor SPDescriptor;
|
|
|
|
// Emit PHI-node-operand constants only once even if used by multiple
|
|
// PHI nodes.
|
|
DenseMap<const Constant *, unsigned> ConstantsOut;
|
|
|
|
/// FuncInfo - Information about the function as a whole.
|
|
///
|
|
FunctionLoweringInfo &FuncInfo;
|
|
|
|
/// OptLevel - What optimization level we're generating code for.
|
|
///
|
|
CodeGenOpt::Level OptLevel;
|
|
|
|
/// GFI - Garbage collection metadata for the function.
|
|
GCFunctionInfo *GFI;
|
|
|
|
/// LPadToCallSiteMap - Map a landing pad to the call site indexes.
|
|
DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
|
|
|
|
/// HasTailCall - This is set to true if a call in the current
|
|
/// block has been translated as a tail call. In this case,
|
|
/// no subsequent DAG nodes should be created.
|
|
///
|
|
bool HasTailCall;
|
|
|
|
LLVMContext *Context;
|
|
|
|
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
|
|
CodeGenOpt::Level ol)
|
|
: CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
|
|
DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
|
|
HasTailCall(false) {
|
|
}
|
|
|
|
void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
|
|
const TargetLibraryInfo *li);
|
|
|
|
/// clear - Clear out the current SelectionDAG and the associated
|
|
/// state and prepare this SelectionDAGBuilder object to be used
|
|
/// for a new block. This doesn't clear out information about
|
|
/// additional blocks that are needed to complete switch lowering
|
|
/// or PHI node updating; that information is cleared out as it is
|
|
/// consumed.
|
|
void clear();
|
|
|
|
/// clearDanglingDebugInfo - Clear the dangling debug information
|
|
/// map. This function is separated from the clear so that debug
|
|
/// information that is dangling in a basic block can be properly
|
|
/// resolved in a different basic block. This allows the
|
|
/// SelectionDAG to resolve dangling debug information attached
|
|
/// to PHI nodes.
|
|
void clearDanglingDebugInfo();
|
|
|
|
/// getRoot - Return the current virtual root of the Selection DAG,
|
|
/// flushing any PendingLoad items. This must be done before emitting
|
|
/// a store or any other node that may need to be ordered after any
|
|
/// prior load instructions.
|
|
///
|
|
SDValue getRoot();
|
|
|
|
/// getControlRoot - Similar to getRoot, but instead of flushing all the
|
|
/// PendingLoad items, flush all the PendingExports items. It is necessary
|
|
/// to do this before emitting a terminator instruction.
|
|
///
|
|
SDValue getControlRoot();
|
|
|
|
SDLoc getCurSDLoc() const {
|
|
return SDLoc(CurInst, SDNodeOrder);
|
|
}
|
|
|
|
DebugLoc getCurDebugLoc() const {
|
|
return CurInst ? CurInst->getDebugLoc() : DebugLoc();
|
|
}
|
|
|
|
unsigned getSDNodeOrder() const { return SDNodeOrder; }
|
|
|
|
void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
|
|
|
|
void visit(const Instruction &I);
|
|
|
|
void visit(unsigned Opcode, const User &I);
|
|
|
|
/// getCopyFromRegs - If there was virtual register allocated for the value V
|
|
/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
|
|
SDValue getCopyFromRegs(const Value *V, Type *Ty);
|
|
|
|
// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
|
|
// generate the debug data structures now that we've seen its definition.
|
|
void resolveDanglingDebugInfo(const Value *V, SDValue Val);
|
|
SDValue getValue(const Value *V);
|
|
bool findValue(const Value *V) const;
|
|
|
|
SDValue getNonRegisterValue(const Value *V);
|
|
SDValue getValueImpl(const Value *V);
|
|
|
|
void setValue(const Value *V, SDValue NewN) {
|
|
SDValue &N = NodeMap[V];
|
|
assert(!N.getNode() && "Already set a value for this node!");
|
|
N = NewN;
|
|
}
|
|
|
|
void setUnusedArgValue(const Value *V, SDValue NewN) {
|
|
SDValue &N = UnusedArgNodeMap[V];
|
|
assert(!N.getNode() && "Already set a value for this node!");
|
|
N = NewN;
|
|
}
|
|
|
|
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
|
|
MachineBasicBlock *SwitchBB, unsigned Opc,
|
|
uint32_t TW, uint32_t FW);
|
|
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
MachineBasicBlock *CurBB,
|
|
MachineBasicBlock *SwitchBB,
|
|
uint32_t TW, uint32_t FW);
|
|
bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
|
|
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
|
|
void CopyToExportRegsIfNeeded(const Value *V);
|
|
void ExportFromCurrentBlock(const Value *V);
|
|
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
|
|
MachineBasicBlock *LandingPad = nullptr);
|
|
|
|
std::pair<SDValue, SDValue> lowerCallOperands(
|
|
ImmutableCallSite CS,
|
|
unsigned ArgIdx,
|
|
unsigned NumArgs,
|
|
SDValue Callee,
|
|
Type *ReturnTy,
|
|
MachineBasicBlock *LandingPad = nullptr,
|
|
bool IsPatchPoint = false);
|
|
|
|
/// UpdateSplitBlock - When an MBB was split during scheduling, update the
|
|
/// references that need to refer to the last resulting block.
|
|
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
|
|
|
|
// This function is responsible for the whole statepoint lowering process.
|
|
// It uniformly handles invoke and call statepoints.
|
|
void LowerStatepoint(ImmutableStatepoint Statepoint,
|
|
MachineBasicBlock *LandingPad = nullptr);
|
|
private:
|
|
std::pair<SDValue, SDValue> lowerInvokable(
|
|
TargetLowering::CallLoweringInfo &CLI,
|
|
MachineBasicBlock *LandingPad);
|
|
|
|
// Terminator instructions.
|
|
void visitRet(const ReturnInst &I);
|
|
void visitBr(const BranchInst &I);
|
|
void visitSwitch(const SwitchInst &I);
|
|
void visitIndirectBr(const IndirectBrInst &I);
|
|
void visitUnreachable(const UnreachableInst &I);
|
|
|
|
uint32_t getEdgeWeight(const MachineBasicBlock *Src,
|
|
const MachineBasicBlock *Dst) const;
|
|
void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
|
|
uint32_t Weight = 0);
|
|
public:
|
|
void visitSwitchCase(CaseBlock &CB,
|
|
MachineBasicBlock *SwitchBB);
|
|
void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
|
|
MachineBasicBlock *ParentBB);
|
|
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
|
|
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
|
|
void visitBitTestCase(BitTestBlock &BB,
|
|
MachineBasicBlock* NextMBB,
|
|
uint32_t BranchWeightToNext,
|
|
unsigned Reg,
|
|
BitTestCase &B,
|
|
MachineBasicBlock *SwitchBB);
|
|
void visitJumpTable(JumpTable &JT);
|
|
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
|
|
MachineBasicBlock *SwitchBB);
|
|
unsigned visitLandingPadClauseBB(GlobalValue *ClauseGV,
|
|
MachineBasicBlock *LPadMBB);
|
|
|
|
private:
|
|
// These all get lowered before this pass.
|
|
void visitInvoke(const InvokeInst &I);
|
|
void visitResume(const ResumeInst &I);
|
|
|
|
void visitBinary(const User &I, unsigned OpCode);
|
|
void visitShift(const User &I, unsigned Opcode);
|
|
void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
|
|
void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
|
|
void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
|
|
void visitFSub(const User &I);
|
|
void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
|
|
void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
|
|
void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
|
|
void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
|
|
void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
|
|
void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
|
|
void visitSDiv(const User &I);
|
|
void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
|
|
void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
|
|
void visitOr (const User &I) { visitBinary(I, ISD::OR); }
|
|
void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
|
|
void visitShl (const User &I) { visitShift(I, ISD::SHL); }
|
|
void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
|
|
void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
|
|
void visitICmp(const User &I);
|
|
void visitFCmp(const User &I);
|
|
// Visit the conversion instructions
|
|
void visitTrunc(const User &I);
|
|
void visitZExt(const User &I);
|
|
void visitSExt(const User &I);
|
|
void visitFPTrunc(const User &I);
|
|
void visitFPExt(const User &I);
|
|
void visitFPToUI(const User &I);
|
|
void visitFPToSI(const User &I);
|
|
void visitUIToFP(const User &I);
|
|
void visitSIToFP(const User &I);
|
|
void visitPtrToInt(const User &I);
|
|
void visitIntToPtr(const User &I);
|
|
void visitBitCast(const User &I);
|
|
void visitAddrSpaceCast(const User &I);
|
|
|
|
void visitExtractElement(const User &I);
|
|
void visitInsertElement(const User &I);
|
|
void visitShuffleVector(const User &I);
|
|
|
|
void visitExtractValue(const ExtractValueInst &I);
|
|
void visitInsertValue(const InsertValueInst &I);
|
|
void visitLandingPad(const LandingPadInst &I);
|
|
|
|
void visitGetElementPtr(const User &I);
|
|
void visitSelect(const User &I);
|
|
|
|
void visitAlloca(const AllocaInst &I);
|
|
void visitLoad(const LoadInst &I);
|
|
void visitStore(const StoreInst &I);
|
|
void visitMaskedLoad(const CallInst &I);
|
|
void visitMaskedStore(const CallInst &I);
|
|
void visitMaskedGather(const CallInst &I);
|
|
void visitMaskedScatter(const CallInst &I);
|
|
void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
|
|
void visitAtomicRMW(const AtomicRMWInst &I);
|
|
void visitFence(const FenceInst &I);
|
|
void visitPHI(const PHINode &I);
|
|
void visitCall(const CallInst &I);
|
|
bool visitMemCmpCall(const CallInst &I);
|
|
bool visitMemChrCall(const CallInst &I);
|
|
bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
|
|
bool visitStrCmpCall(const CallInst &I);
|
|
bool visitStrLenCall(const CallInst &I);
|
|
bool visitStrNLenCall(const CallInst &I);
|
|
bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
|
|
bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
|
|
void visitAtomicLoad(const LoadInst &I);
|
|
void visitAtomicStore(const StoreInst &I);
|
|
|
|
void visitInlineAsm(ImmutableCallSite CS);
|
|
const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
|
|
void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
|
|
|
|
void visitVAStart(const CallInst &I);
|
|
void visitVAArg(const VAArgInst &I);
|
|
void visitVAEnd(const CallInst &I);
|
|
void visitVACopy(const CallInst &I);
|
|
void visitStackmap(const CallInst &I);
|
|
void visitPatchpoint(ImmutableCallSite CS,
|
|
MachineBasicBlock *LandingPad = nullptr);
|
|
|
|
// These three are implemented in StatepointLowering.cpp
|
|
void visitStatepoint(const CallInst &I);
|
|
void visitGCRelocate(const CallInst &I);
|
|
void visitGCResult(const CallInst &I);
|
|
|
|
void visitUserOp1(const Instruction &I) {
|
|
llvm_unreachable("UserOp1 should not exist at instruction selection time!");
|
|
}
|
|
void visitUserOp2(const Instruction &I) {
|
|
llvm_unreachable("UserOp2 should not exist at instruction selection time!");
|
|
}
|
|
|
|
void processIntegerCallValue(const Instruction &I,
|
|
SDValue Value, bool IsSigned);
|
|
|
|
void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
|
|
|
|
/// EmitFuncArgumentDbgValue - If V is an function argument then create
|
|
/// corresponding DBG_VALUE machine instruction for it now. At the end of
|
|
/// instruction selection, they will be inserted to the entry BB.
|
|
bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
|
|
DIExpression *Expr, DILocation *DL,
|
|
int64_t Offset, bool IsIndirect,
|
|
const SDValue &N);
|
|
|
|
/// Return the next block after MBB, or nullptr if there is none.
|
|
MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
|
|
|
|
/// Update the DAG and DAG builder with the relevant information after
|
|
/// a new root node has been created which could be a tail call.
|
|
void updateDAGForMaybeTailCall(SDValue MaybeTC);
|
|
};
|
|
|
|
/// RegsForValue - This struct represents the registers (physical or virtual)
|
|
/// that a particular set of values is assigned, and the type information about
|
|
/// the value. The most common situation is to represent one value at a time,
|
|
/// but struct or array values are handled element-wise as multiple values. The
|
|
/// splitting of aggregates is performed recursively, so that we never have
|
|
/// aggregate-typed registers. The values at this point do not necessarily have
|
|
/// legal types, so each value may require one or more registers of some legal
|
|
/// type.
|
|
///
|
|
struct RegsForValue {
|
|
/// ValueVTs - The value types of the values, which may not be legal, and
|
|
/// may need be promoted or synthesized from one or more registers.
|
|
///
|
|
SmallVector<EVT, 4> ValueVTs;
|
|
|
|
/// RegVTs - The value types of the registers. This is the same size as
|
|
/// ValueVTs and it records, for each value, what the type of the assigned
|
|
/// register or registers are. (Individual values are never synthesized
|
|
/// from more than one type of register.)
|
|
///
|
|
/// With virtual registers, the contents of RegVTs is redundant with TLI's
|
|
/// getRegisterType member function, however when with physical registers
|
|
/// it is necessary to have a separate record of the types.
|
|
///
|
|
SmallVector<MVT, 4> RegVTs;
|
|
|
|
/// Regs - This list holds the registers assigned to the values.
|
|
/// Each legal or promoted value requires one register, and each
|
|
/// expanded value requires multiple registers.
|
|
///
|
|
SmallVector<unsigned, 4> Regs;
|
|
|
|
RegsForValue();
|
|
|
|
RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt);
|
|
|
|
RegsForValue(LLVMContext &Context, const TargetLowering &tli, unsigned Reg,
|
|
Type *Ty);
|
|
|
|
/// append - Add the specified values to this one.
|
|
void append(const RegsForValue &RHS) {
|
|
ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
|
|
RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
|
|
Regs.append(RHS.Regs.begin(), RHS.Regs.end());
|
|
}
|
|
|
|
/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
|
|
/// this value and returns the result as a ValueVTs value. This uses
|
|
/// Chain/Flag as the input and updates them for the output Chain/Flag.
|
|
/// If the Flag pointer is NULL, no flag is used.
|
|
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
|
|
SDLoc dl,
|
|
SDValue &Chain, SDValue *Flag,
|
|
const Value *V = nullptr) const;
|
|
|
|
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified
|
|
/// value into the registers specified by this object. This uses Chain/Flag
|
|
/// as the input and updates them for the output Chain/Flag. If the Flag
|
|
/// pointer is nullptr, no flag is used. If V is not nullptr, then it is used
|
|
/// in printing better diagnostic messages on error.
|
|
void
|
|
getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
|
|
SDValue *Flag, const Value *V = nullptr,
|
|
ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
|
|
|
|
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
|
|
/// operand list. This adds the code marker, matching input operand index
|
|
/// (if applicable), and includes the number of values added into it.
|
|
void AddInlineAsmOperands(unsigned Kind,
|
|
bool HasMatching, unsigned MatchingIdx, SDLoc dl,
|
|
SelectionDAG &DAG,
|
|
std::vector<SDValue> &Ops) const;
|
|
};
|
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} // end namespace llvm
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#endif
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