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a04fe83378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155797 91177308-0d34-0410-b5e6-96231b3b80d8
107 lines
3.9 KiB
Plaintext
107 lines
3.9 KiB
Plaintext
//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//
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This code was contributed by a team from the Computer Systems Research
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Department in The Aerospace Corporation:
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- Scott Michel (head bottle washer and much of the non-floating point
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instructions)
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- Mark Thomas (floating point instructions)
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- Michael AuYeung (intrinsics)
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- Chandler Carruth (LLVM expertise)
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- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)
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Some minor fixes added by Kalle Raiskila.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
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OTHERWISE. IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
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OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
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OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
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LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
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REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
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OR PUNITIVE DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
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SUCH DAMAGES ARE FORESEEABLE.
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---------------------------------------------------------------------------
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--WARNING--:
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--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
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--WARNING--:
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If you are brave enough to try this code or help to hack on it, be sure
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to add 'spu' to configure's --enable-targets option, e.g.:
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./configure <your_configure_flags_here> \
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--enable-targets=x86,x86_64,powerpc,spu
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---------------------------------------------------------------------------
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TODO:
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* In commit r142152 vector legalization was set to element promotion per
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default. This breaks half vectors (e.g. v2i32) badly as they get element
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promoted to much slower types (v2i64).
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* Many CellSPU specific codegen tests only grep & count the number of
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instructions, not checking their place with FileCheck. There have also
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been some commits that change the CellSPU checks, some of which might
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have not been thoroughly scrutinized w.r.t. to the changes they cause in SPU
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assembly. (especially since about the time of r142152)
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* Some of the i64 math have huge tablegen rules, which sometime cause
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tablegen to run out of memory. See e.g. bug 8850. i64 arithmetics
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should probably be done with libraries.
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* Create a machine pass for performing dual-pipeline scheduling specifically
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for CellSPU, and insert branch prediction instructions as needed.
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* i32 instructions:
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* i32 division (work-in-progress)
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* i64 support (see i64operations.c test harness):
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* shifts and comparison operators: done
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* sign and zero extension: done
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* addition: done
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* subtraction: needed
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* multiplication: done
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* i128 support:
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* zero extension, any extension: done
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* sign extension: done
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* arithmetic operators (add, sub, mul, div): needed
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* logical operations (and, or, shl, srl, sra, xor, nor, nand): needed
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* or: done
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* f64 support
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* Comparison operators:
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SETOEQ unimplemented
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SETOGT unimplemented
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SETOGE unimplemented
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SETOLT unimplemented
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SETOLE unimplemented
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SETONE unimplemented
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SETO done (lowered)
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SETUO done (lowered)
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SETUEQ unimplemented
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SETUGT unimplemented
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SETUGE unimplemented
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SETULT unimplemented
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SETULE unimplemented
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SETUNE unimplemented
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* LLVM vector suport
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* VSETCC needs to be implemented. It's pretty straightforward to code, but
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needs implementation.
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* Intrinsics
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* spu.h instrinsics added but not tested. Need to have an operational
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llvm-spu-gcc in order to write a unit test harness.
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===-------------------------------------------------------------------------===
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