llvm-6502/test/CodeGen
Andrew Trick eaf8a32859 Add a limit to the heuristic that register allocates instructions in local order.
This handles pathological cases in which we see 2x increase in spill
code for large blocks (~50k instructions). I don't have a unit test
for this behavior.

Fixes rdar://16072279.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202304 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 22:07:26 +00:00
..
AArch64 AArch64: simplify tbl/tbx polymorphism 2014-02-26 11:55:09 +00:00
ARM Stop test/CodeGen/ARM/a15.ll targetting non-ARM targets. 2014-02-26 11:26:18 +00:00
CPP
Generic
Hexagon
Inputs
Mips
MSP430
NVPTX
PowerPC Account for 128-bit integer operations in PPCCTRLoops 2014-02-25 20:51:50 +00:00
R600 R600/SI: Custom select 64-bit ADD 2014-02-25 21:36:18 +00:00
SPARC SPARC: Implement TRAP lowering. Matches what GCC emits. 2014-02-23 21:43:52 +00:00
SystemZ
Thumb
Thumb2 ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block 2014-02-26 11:27:28 +00:00
X86 Add a limit to the heuristic that register allocates instructions in local order. 2014-02-26 22:07:26 +00:00
XCore [XCore] Add intrinsic for CLRPT (clear port time) instruction. 2014-02-25 17:31:15 +00:00