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eb01abaad1
Clone functions that are shared between the Main thread and Interrupt thread. CallSites are changed in AsmPrinter currently. A better solution would have been to modify the legalizer (SoftenFloat) to allow targets to change the name of libcalls for float operations. But that currently breaks other targets. Also, cloing of automatic variables is done AsmPrinter, a better approach would be to use the ValueMap in CloneFunction itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79562 91177308-0d34-0410-b5e6-96231b3b80d8
256 lines
10 KiB
C++
256 lines
10 KiB
C++
//===-- PIC16ISelLowering.h - PIC16 DAG Lowering Interface ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that PIC16 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PIC16ISELLOWERING_H
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#define PIC16ISELLOWERING_H
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#include "PIC16.h"
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#include "PIC16Subtarget.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include <map>
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namespace llvm {
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namespace PIC16ISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Lo, // Low 8-bits of GlobalAddress.
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Hi, // High 8-bits of GlobalAddress.
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PIC16Load,
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PIC16LdArg, // This is replica of PIC16Load but used to load function
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// arguments and is being used for facilitating for some
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// store removal optimizations.
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PIC16LdWF,
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PIC16Store,
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PIC16StWF,
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Banksel,
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MTLO, // Move to low part of FSR
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MTHI, // Move to high part of FSR
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MTPCLATH, // Move to PCLATCH
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PIC16Connect, // General connector for PIC16 nodes
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BCF,
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LSLF, // PIC16 Logical shift left
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LRLF, // PIC16 Logical shift right
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RLF, // Rotate left through carry
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RRF, // Rotate right through carry
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CALL, // PIC16 Call instruction
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CALLW, // PIC16 CALLW instruction
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SUBCC, // Compare for equality or inequality.
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SELECT_ICC, // Psuedo to be caught in schedular and expanded to brcond.
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BRCOND, // Conditional branch.
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RET, // Return.
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RETFIE, // Return from interrupt
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Dummy
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};
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// Keep track of different address spaces.
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enum AddressSpace {
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RAM_SPACE = 0, // RAM address space
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ROM_SPACE = 1 // ROM address space number is 1
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};
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enum PIC16Libcall {
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MUL_I8 = RTLIB::UNKNOWN_LIBCALL + 1,
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SRA_I8,
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SLL_I8,
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SRL_I8,
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PIC16UnknownCall
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class PIC16TargetLowering : public TargetLowering {
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public:
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explicit PIC16TargetLowering(PIC16TargetMachine &TM);
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - Return the ISD::SETCC ValueType
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virtual MVT::SimpleValueType getSetCCResultType(EVT ValType) const;
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SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
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SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
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SDValue LowerADD(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSUB(SDValue Op, SelectionDAG &DAG);
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SDValue LowerBinOp(SDValue Op, SelectionDAG &DAG);
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// Call returns
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SDValue
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LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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SDValue
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LowerIndirectCallReturn(SDValue Chain, SDValue InFlag,
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SDValue DataAddr_Lo, SDValue DataAddr_Hi,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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// Call arguments
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SDValue
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LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG);
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SDValue
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LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
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SDValue DataAddr_Lo, SDValue DataAddr_Hi,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG);
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
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SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC,
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SelectionDAG &DAG, DebugLoc dl);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
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virtual void ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG);
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virtual void LowerOperationWrapper(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG);
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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unsigned CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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unsigned CallConv, bool isVarArg, bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals);
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virtual SDValue
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LowerReturn(SDValue Chain,
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unsigned CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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DebugLoc dl, SelectionDAG &DAG);
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SDValue ExpandStore(SDNode *N, SelectionDAG &DAG);
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SDValue ExpandLoad(SDNode *N, SelectionDAG &DAG);
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SDValue ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG);
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SDValue ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG);
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SDValue ExpandFrameIndex(SDNode *N, SelectionDAG &DAG);
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue PerformStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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// This function returns the Tmp Offset for FrameIndex. If any TmpOffset
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// already exists for the FI then it returns the same else it creates the
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// new offset and returns.
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unsigned GetTmpOffsetForFI(unsigned FI, unsigned slot_size);
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void ResetTmpOffsetMap() { FiTmpOffsetMap.clear(); SetTmpSize(0); }
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void InitReservedFrameCount(const Function *F);
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// Return the size of Tmp variable
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unsigned GetTmpSize() { return TmpSize; }
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void SetTmpSize(unsigned Size) { TmpSize = Size; }
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *) const {
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// FIXME: The function never seems to be aligned.
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return 1;
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}
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private:
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// If the Node is a BUILD_PAIR representing a direct Address,
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// then this function will return true.
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bool isDirectAddress(const SDValue &Op);
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// If the Node is a DirectAddress in ROM_SPACE then this
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// function will return true
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bool isRomAddress(const SDValue &Op);
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// Extract the Lo and Hi component of Op.
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void GetExpandedParts(SDValue Op, SelectionDAG &DAG, SDValue &Lo,
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SDValue &Hi);
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// Load pointer can be a direct or indirect address. In PIC16 direct
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// addresses need Banksel and Indirect addresses need to be loaded to
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// FSR first. Handle address specific cases here.
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void LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Chain,
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SDValue &NewPtr, unsigned &Offset, DebugLoc dl);
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// FrameIndex should be broken down into ExternalSymbol and FrameOffset.
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void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES,
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int &Offset);
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// For indirect calls data address of the callee frame need to be
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// extracted. This function fills the arguments DataAddr_Lo and
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// DataAddr_Hi with the address of the callee frame.
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void GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
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SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
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SelectionDAG &DAG);
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// We can not have both operands of a binary operation in W.
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// This function is used to put one operand on stack and generate a load.
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SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
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// This function checks if we need to put an operand of an operation on
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// stack and generate a load or not.
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bool NeedToConvertToMemOp(SDValue Op, unsigned &MemOp);
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/// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const PIC16Subtarget *Subtarget;
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// Extending the LIB Call framework of LLVM
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// to hold the names of PIC16Libcalls.
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const char *PIC16LibcallNames[PIC16ISD::PIC16UnknownCall];
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// To set and retrieve the lib call names.
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void setPIC16LibcallName(PIC16ISD::PIC16Libcall Call, const char *Name);
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const char *getPIC16LibcallName(PIC16ISD::PIC16Libcall Call);
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// Make PIC16 Libcall.
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SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, EVT RetVT,
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const SDValue *Ops, unsigned NumOps, bool isSigned,
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SelectionDAG &DAG, DebugLoc dl);
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// Check if operation has a direct load operand.
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inline bool isDirectLoad(const SDValue Op);
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private:
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// The frameindexes generated for spill/reload are stack based.
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// This maps maintain zero based indexes for these FIs.
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std::map<unsigned, unsigned> FiTmpOffsetMap;
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unsigned TmpSize;
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// These are the frames for return value and argument passing
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// These FrameIndices will be expanded to foo.frame external symbol
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// and all others will be expanded to foo.tmp external symbol.
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unsigned ReservedFrameCount;
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};
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} // namespace llvm
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#endif // PIC16ISELLOWERING_H
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