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https://github.com/c64scene-ar/llvm-6502.git
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using the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210595 91177308-0d34-0410-b5e6-96231b3b80d8
733 lines
26 KiB
C++
733 lines
26 KiB
C++
//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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// This file is responsible for the frame pointer elimination optimization
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// on X86.
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//
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//===----------------------------------------------------------------------===//
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#include "X86RegisterInfo.h"
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#include "X86InstrBuilder.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define GET_REGINFO_TARGET_DESC
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#include "X86GenRegisterInfo.inc"
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cl::opt<bool>
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ForceStackAlign("force-align-stack",
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cl::desc("Force align the stack to the minimum alignment"
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" needed for the function."),
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cl::init(false), cl::Hidden);
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static cl::opt<bool>
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EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
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cl::desc("Enable use of a base pointer for complex stack frames"));
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X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
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: X86GenRegisterInfo(
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(STI.is64Bit() ? X86::RIP : X86::EIP),
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X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
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X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
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(STI.is64Bit() ? X86::RIP : X86::EIP)),
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Subtarget(STI) {
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X86_MC::InitLLVM2SEHRegisterMapping(this);
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// Cache some information.
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Is64Bit = Subtarget.is64Bit();
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IsWin64 = Subtarget.isTargetWin64();
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if (Is64Bit) {
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SlotSize = 8;
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StackPtr = X86::RSP;
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FramePtr = X86::RBP;
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} else {
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SlotSize = 4;
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StackPtr = X86::ESP;
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FramePtr = X86::EBP;
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}
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// Use a callee-saved register as the base pointer. These registers must
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// not conflict with any ABI requirements. For example, in 32-bit mode PIC
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// requires GOT in the EBX register before function calls via PLT GOT pointer.
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BasePtr = Is64Bit ? X86::RBX : X86::ESI;
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}
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/// getCompactUnwindRegNum - This function maps the register to the number for
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/// compact unwind encoding. Return -1 if the register isn't valid.
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int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
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switch (getLLVMRegNum(RegNum, isEH)) {
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case X86::EBX: case X86::RBX: return 1;
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case X86::ECX: case X86::R12: return 2;
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case X86::EDX: case X86::R13: return 3;
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case X86::EDI: case X86::R14: return 4;
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case X86::ESI: case X86::R15: return 5;
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case X86::EBP: case X86::RBP: return 6;
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}
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return -1;
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}
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bool
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X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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// ExeDepsFixer and PostRAScheduler require liveness.
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return true;
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}
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int
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X86RegisterInfo::getSEHRegNum(unsigned i) const {
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return getEncodingValue(i);
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}
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const TargetRegisterClass *
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X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
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unsigned Idx) const {
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// The sub_8bit sub-register index is more constrained in 32-bit mode.
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// It behaves just like the sub_8bit_hi index.
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if (!Is64Bit && Idx == X86::sub_8bit)
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Idx = X86::sub_8bit_hi;
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// Forward to TableGen's default version.
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return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
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}
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const TargetRegisterClass *
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X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned SubIdx) const {
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// The sub_8bit sub-register index is more constrained in 32-bit mode.
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if (!Is64Bit && SubIdx == X86::sub_8bit) {
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A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
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if (!A)
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return nullptr;
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}
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return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
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}
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const TargetRegisterClass*
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X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
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// Don't allow super-classes of GR8_NOREX. This class is only used after
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// extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
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// to the full GR8 register class in 64-bit mode, so we cannot allow the
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// reigster class inflation.
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//
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// The GR8_NOREX class is always used in a way that won't be constrained to a
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// sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
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// full GR8 class.
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if (RC == &X86::GR8_NOREXRegClass)
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return RC;
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const TargetRegisterClass *Super = RC;
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TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
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do {
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switch (Super->getID()) {
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case X86::GR8RegClassID:
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case X86::GR16RegClassID:
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case X86::GR32RegClassID:
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case X86::GR64RegClassID:
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case X86::FR32RegClassID:
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case X86::FR64RegClassID:
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case X86::RFP32RegClassID:
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case X86::RFP64RegClassID:
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case X86::RFP80RegClassID:
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case X86::VR128RegClassID:
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case X86::VR256RegClassID:
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// Don't return a super-class that would shrink the spill size.
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// That can happen with the vector and float classes.
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if (Super->getSize() == RC->getSize())
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return Super;
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}
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Super = *I++;
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} while (Super);
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return RC;
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}
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const TargetRegisterClass *
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X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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switch (Kind) {
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default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
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case 0: // Normal GPRs.
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if (Subtarget.isTarget64BitLP64())
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return &X86::GR64RegClass;
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return &X86::GR32RegClass;
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case 1: // Normal GPRs except the stack pointer (for encoding reasons).
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if (Subtarget.isTarget64BitLP64())
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return &X86::GR64_NOSPRegClass;
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return &X86::GR32_NOSPRegClass;
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case 2: // Available for tailcall (not callee-saved GPRs).
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if (Subtarget.isTargetWin64())
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return &X86::GR64_TCW64RegClass;
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else if (Subtarget.is64Bit())
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return &X86::GR64_TCRegClass;
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const Function *F = MF.getFunction();
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bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
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if (hasHipeCC)
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return &X86::GR32RegClass;
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return &X86::GR32_TCRegClass;
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}
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}
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const TargetRegisterClass *
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X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
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if (RC == &X86::CCRRegClass) {
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if (Is64Bit)
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return &X86::GR64RegClass;
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else
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return &X86::GR32RegClass;
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}
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return RC;
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}
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unsigned
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X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
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switch (RC->getID()) {
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default:
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return 0;
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case X86::GR32RegClassID:
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return 4 - FPDiff;
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case X86::GR64RegClassID:
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return 12 - FPDiff;
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case X86::VR128RegClassID:
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return Subtarget.is64Bit() ? 10 : 4;
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case X86::VR64RegClassID:
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return 4;
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}
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}
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const MCPhysReg *
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X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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bool HasAVX = Subtarget.hasAVX();
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bool HasAVX512 = Subtarget.hasAVX512();
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assert(MF && "MachineFunction required");
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switch (MF->getFunction()->getCallingConv()) {
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case CallingConv::GHC:
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case CallingConv::HiPE:
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return CSR_NoRegs_SaveList;
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case CallingConv::AnyReg:
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if (HasAVX)
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return CSR_64_AllRegs_AVX_SaveList;
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return CSR_64_AllRegs_SaveList;
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case CallingConv::PreserveMost:
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return CSR_64_RT_MostRegs_SaveList;
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case CallingConv::PreserveAll:
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if (HasAVX)
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return CSR_64_RT_AllRegs_AVX_SaveList;
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return CSR_64_RT_AllRegs_SaveList;
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case CallingConv::Intel_OCL_BI: {
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if (HasAVX512 && IsWin64)
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return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
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if (HasAVX512 && Is64Bit)
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return CSR_64_Intel_OCL_BI_AVX512_SaveList;
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if (HasAVX && IsWin64)
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return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
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if (HasAVX && Is64Bit)
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return CSR_64_Intel_OCL_BI_AVX_SaveList;
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if (!HasAVX && !IsWin64 && Is64Bit)
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return CSR_64_Intel_OCL_BI_SaveList;
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break;
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}
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case CallingConv::Cold:
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if (Is64Bit)
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return CSR_64_MostRegs_SaveList;
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break;
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default:
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break;
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}
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bool CallsEHReturn = MF->getMMI().callsEHReturn();
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if (Is64Bit) {
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if (IsWin64)
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return CSR_Win64_SaveList;
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if (CallsEHReturn)
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return CSR_64EHRet_SaveList;
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return CSR_64_SaveList;
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}
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if (CallsEHReturn)
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return CSR_32EHRet_SaveList;
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return CSR_32_SaveList;
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}
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const uint32_t*
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X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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bool HasAVX = Subtarget.hasAVX();
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bool HasAVX512 = Subtarget.hasAVX512();
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switch (CC) {
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case CallingConv::GHC:
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case CallingConv::HiPE:
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return CSR_NoRegs_RegMask;
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case CallingConv::AnyReg:
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if (HasAVX)
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return CSR_64_AllRegs_AVX_RegMask;
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return CSR_64_AllRegs_RegMask;
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case CallingConv::PreserveMost:
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return CSR_64_RT_MostRegs_RegMask;
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case CallingConv::PreserveAll:
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if (HasAVX)
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return CSR_64_RT_AllRegs_AVX_RegMask;
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return CSR_64_RT_AllRegs_RegMask;
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case CallingConv::Intel_OCL_BI: {
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if (HasAVX512 && IsWin64)
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return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
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if (HasAVX512 && Is64Bit)
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return CSR_64_Intel_OCL_BI_AVX512_RegMask;
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if (HasAVX && IsWin64)
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return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
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if (HasAVX && Is64Bit)
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return CSR_64_Intel_OCL_BI_AVX_RegMask;
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if (!HasAVX && !IsWin64 && Is64Bit)
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return CSR_64_Intel_OCL_BI_RegMask;
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break;
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}
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case CallingConv::Cold:
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if (Is64Bit)
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return CSR_64_MostRegs_RegMask;
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break;
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default:
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break;
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}
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// Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
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// callsEHReturn().
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if (Is64Bit) {
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if (IsWin64)
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return CSR_Win64_RegMask;
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return CSR_64_RegMask;
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}
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return CSR_32_RegMask;
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}
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const uint32_t*
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X86RegisterInfo::getNoPreservedMask() const {
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return CSR_NoRegs_RegMask;
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}
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BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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// Set the stack-pointer register and its aliases as reserved.
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for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
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++I)
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Reserved.set(*I);
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// Set the instruction pointer register and its aliases as reserved.
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for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
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++I)
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Reserved.set(*I);
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// Set the frame-pointer register and its aliases as reserved if needed.
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if (TFI->hasFP(MF)) {
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for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
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++I)
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Reserved.set(*I);
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}
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// Set the base-pointer register and its aliases as reserved if needed.
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if (hasBasePointer(MF)) {
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CallingConv::ID CC = MF.getFunction()->getCallingConv();
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const uint32_t* RegMask = getCallPreservedMask(CC);
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if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
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report_fatal_error(
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"Stack realignment in presence of dynamic allocas is not supported with"
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"this calling convention.");
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for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
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I.isValid(); ++I)
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Reserved.set(*I);
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}
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// Mark the segment registers as reserved.
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Reserved.set(X86::CS);
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Reserved.set(X86::SS);
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Reserved.set(X86::DS);
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Reserved.set(X86::ES);
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Reserved.set(X86::FS);
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Reserved.set(X86::GS);
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// Mark the floating point stack registers as reserved.
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for (unsigned n = 0; n != 8; ++n)
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Reserved.set(X86::ST0 + n);
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// Reserve the registers that only exist in 64-bit mode.
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if (!Is64Bit) {
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// These 8-bit registers are part of the x86-64 extension even though their
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// super-registers are old 32-bits.
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Reserved.set(X86::SIL);
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Reserved.set(X86::DIL);
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Reserved.set(X86::BPL);
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Reserved.set(X86::SPL);
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for (unsigned n = 0; n != 8; ++n) {
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// R8, R9, ...
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for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
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Reserved.set(*AI);
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// XMM8, XMM9, ...
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for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
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Reserved.set(*AI);
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}
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}
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if (!Is64Bit || !Subtarget.hasAVX512()) {
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for (unsigned n = 16; n != 32; ++n) {
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for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
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Reserved.set(*AI);
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}
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}
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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if (!EnableBasePointer)
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return false;
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// When we need stack realignment, we can't address the stack from the frame
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// pointer. When we have dynamic allocas or stack-adjusting inline asm, we
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// can't address variables from the stack pointer. MS inline asm can
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// reference locals while also adjusting the stack pointer. When we can't
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// use both the SP and the FP, we need a separate base pointer register.
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bool CantUseFP = needsStackRealignment(MF);
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bool CantUseSP =
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MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
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return CantUseFP && CantUseSP;
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}
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bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
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if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
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return false;
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const MachineRegisterInfo *MRI = &MF.getRegInfo();
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// Stack realignment requires a frame pointer. If we already started
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// register allocation with frame pointer elimination, it is too late now.
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if (!MRI->canReserveReg(FramePtr))
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return false;
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// If a base pointer is necessary. Check that it isn't too late to reserve
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// it.
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if (MFI->hasVarSizedObjects())
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return MRI->canReserveReg(BasePtr);
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return true;
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}
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bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const Function *F = MF.getFunction();
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unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
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bool requiresRealignment =
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((MFI->getMaxAlignment() > StackAlign) ||
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F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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Attribute::StackAlignment));
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// If we've requested that we force align the stack do so now.
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if (ForceStackAlign)
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return canRealignStack(MF);
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|
return requiresRealignment && canRealignStack(MF);
|
|
}
|
|
|
|
bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
|
|
unsigned Reg, int &FrameIdx) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
if (Reg == FramePtr && TFI->hasFP(MF)) {
|
|
FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void
|
|
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, unsigned FIOperandNum,
|
|
RegScavenger *RS) const {
|
|
assert(SPAdj == 0 && "Unexpected");
|
|
|
|
MachineInstr &MI = *II;
|
|
MachineFunction &MF = *MI.getParent()->getParent();
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
|
|
unsigned BasePtr;
|
|
|
|
unsigned Opc = MI.getOpcode();
|
|
bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
|
|
if (hasBasePointer(MF))
|
|
BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
|
|
else if (needsStackRealignment(MF))
|
|
BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
|
|
else if (AfterFPPop)
|
|
BasePtr = StackPtr;
|
|
else
|
|
BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
|
|
|
|
// This must be part of a four operand memory reference. Replace the
|
|
// FrameIndex with base register with EBP. Add an offset to the offset.
|
|
MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
|
|
|
|
// Now add the frame object offset to the offset from EBP.
|
|
int FIOffset;
|
|
if (AfterFPPop) {
|
|
// Tail call jmp happens after FP is popped.
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
|
|
} else
|
|
FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
|
|
|
|
// The frame index format for stackmaps and patchpoints is different from the
|
|
// X86 format. It only has a FI and an offset.
|
|
if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
|
|
assert(BasePtr == FramePtr && "Expected the FP as base register");
|
|
int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
|
|
MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
|
|
return;
|
|
}
|
|
|
|
if (MI.getOperand(FIOperandNum+3).isImm()) {
|
|
// Offset is a 32-bit integer.
|
|
int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
|
|
int Offset = FIOffset + Imm;
|
|
assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|
|
"Requesting 64-bit offset in 32-bit immediate!");
|
|
MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
|
|
} else {
|
|
// Offset is symbolic. This is extremely rare.
|
|
uint64_t Offset = FIOffset +
|
|
(uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
|
|
MI.getOperand(FIOperandNum + 3).setOffset(Offset);
|
|
}
|
|
}
|
|
|
|
unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
return TFI->hasFP(MF) ? FramePtr : StackPtr;
|
|
}
|
|
|
|
namespace llvm {
|
|
unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
|
|
bool High) {
|
|
switch (VT) {
|
|
default: llvm_unreachable("Unexpected VT");
|
|
case MVT::i8:
|
|
if (High) {
|
|
switch (Reg) {
|
|
default: return getX86SubSuperRegister(Reg, MVT::i64);
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SP;
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AH;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DH;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CH;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BH;
|
|
}
|
|
} else {
|
|
switch (Reg) {
|
|
default: llvm_unreachable("Unexpected register");
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AL;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DL;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CL;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BL;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SIL;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DIL;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BPL;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SPL;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8B;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9B;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10B;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11B;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12B;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13B;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14B;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15B;
|
|
}
|
|
}
|
|
case MVT::i16:
|
|
switch (Reg) {
|
|
default: llvm_unreachable("Unexpected register");
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::AX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::DX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::CX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::BX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::SI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::DI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::BP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::SP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8W;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9W;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10W;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11W;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12W;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13W;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14W;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15W;
|
|
}
|
|
case MVT::i32:
|
|
switch (Reg) {
|
|
default: llvm_unreachable("Unexpected register");
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::EAX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::EDX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::ECX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::EBX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::ESI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::EDI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::EBP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::ESP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8D;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9D;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10D;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11D;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12D;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13D;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14D;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15D;
|
|
}
|
|
case MVT::i64:
|
|
switch (Reg) {
|
|
default: llvm_unreachable("Unexpected register");
|
|
case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
|
|
return X86::RAX;
|
|
case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
|
|
return X86::RDX;
|
|
case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
|
|
return X86::RCX;
|
|
case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
|
return X86::RBX;
|
|
case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
|
|
return X86::RSI;
|
|
case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
|
|
return X86::RDI;
|
|
case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
|
|
return X86::RBP;
|
|
case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
|
|
return X86::RSP;
|
|
case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
|
|
return X86::R8;
|
|
case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
|
|
return X86::R9;
|
|
case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
|
|
return X86::R10;
|
|
case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
|
|
return X86::R11;
|
|
case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
|
|
return X86::R12;
|
|
case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
|
|
return X86::R13;
|
|
case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
|
|
return X86::R14;
|
|
case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
|
|
return X86::R15;
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned get512BitSuperRegister(unsigned Reg) {
|
|
if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
|
|
return X86::ZMM0 + (Reg - X86::XMM0);
|
|
if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
|
|
return X86::ZMM0 + (Reg - X86::YMM0);
|
|
if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
|
|
return Reg;
|
|
llvm_unreachable("Unexpected SIMD register");
|
|
}
|
|
|
|
}
|