mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
0b8c9a80f2
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.9 KiB
C++
60 lines
1.9 KiB
C++
//===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "MipsMachineFunction.h"
|
|
#include "MCTargetDesc/MipsBaseInfo.h"
|
|
#include "MipsInstrInfo.h"
|
|
#include "MipsSubtarget.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
#include "llvm/IR/Function.h"
|
|
#include "llvm/Support/CommandLine.h"
|
|
|
|
using namespace llvm;
|
|
|
|
static cl::opt<bool>
|
|
FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
|
|
cl::desc("Always use $gp as the global base register."));
|
|
|
|
bool MipsFunctionInfo::globalBaseRegSet() const {
|
|
return GlobalBaseReg;
|
|
}
|
|
|
|
unsigned MipsFunctionInfo::getGlobalBaseReg() {
|
|
// Return if it has already been initialized.
|
|
if (GlobalBaseReg)
|
|
return GlobalBaseReg;
|
|
|
|
const MipsSubtarget &ST = MF.getTarget().getSubtarget<MipsSubtarget>();
|
|
|
|
const TargetRegisterClass *RC;
|
|
if (ST.inMips16Mode())
|
|
RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
|
|
else
|
|
RC = ST.isABI_N64() ?
|
|
(const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
|
|
(const TargetRegisterClass*)&Mips::CPURegsRegClass;
|
|
return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
|
|
}
|
|
|
|
bool MipsFunctionInfo::mips16SPAliasRegSet() const {
|
|
return Mips16SPAliasReg;
|
|
}
|
|
unsigned MipsFunctionInfo::getMips16SPAliasReg() {
|
|
// Return if it has already been initialized.
|
|
if (Mips16SPAliasReg)
|
|
return Mips16SPAliasReg;
|
|
|
|
const TargetRegisterClass *RC;
|
|
RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
|
|
return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
|
|
}
|
|
|
|
void MipsFunctionInfo::anchor() { }
|