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https://github.com/c64scene-ar/llvm-6502.git
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a9bd4b4647
register for inline asm. This conforms to how gcc allows for effective casting of inputs into gprs (fprs is already handled). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174008 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
1.6 KiB
LLVM
43 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - | FileCheck %s
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; C code this came from
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;bool cas(float volatile *p, float *expected, float desired) {
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; bool success;
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; __asm__ __volatile__("lock; cmpxchg %[desired], %[mem]; "
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; "mov %[expected], %[expected_out]; "
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; "sete %[success]"
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; : [success] "=a" (success),
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; [expected_out] "=rm" (*expected)
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; : [expected] "a" (*expected),
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; [desired] "q" (desired),
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; [mem] "m" (*p)
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; : "memory", "cc");
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; return success;
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;}
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define zeroext i1 @cas(float* %p, float* %expected, float %desired) nounwind {
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entry:
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%p.addr = alloca float*, align 8
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%expected.addr = alloca float*, align 8
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%desired.addr = alloca float, align 4
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%success = alloca i8, align 1
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store float* %p, float** %p.addr, align 8
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store float* %expected, float** %expected.addr, align 8
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store float %desired, float* %desired.addr, align 4
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%0 = load float** %expected.addr, align 8
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%1 = load float** %expected.addr, align 8
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%2 = load float* %1, align 4
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%3 = load float* %desired.addr, align 4
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%4 = load float** %p.addr, align 8
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%5 = call i8 asm sideeffect "lock; cmpxchg $3, $4; mov $2, $1; sete $0", "={ax},=*rm,{ax},q,*m,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(float* %0, float %2, float %3, float* %4) nounwind
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store i8 %5, i8* %success, align 1
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%6 = load i8* %success, align 1
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%tobool = trunc i8 %6 to i1
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ret i1 %tobool
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}
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; Make sure we're emitting a move from
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; CHECK: #APP
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; CHECK-NEXT: lock;{{.*}}mov %eax,{{.*}}
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; CHECK-NEXT: #NO_APP
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