mirror of
https://github.com/c64scene-ar/llvm-6502.git
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27b1252c13
This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
4.5 KiB
LLVM
144 lines
4.5 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s
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; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -regalloc=basic %s -o - \
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; RUN: | FileCheck %s
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define <8 x i8> @vld1i8(i8* %A) nounwind {
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;CHECK-LABEL: vld1i8:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vld1.8 {d16}, [r0:64]
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%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
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ret <8 x i8> %tmp1
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}
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define <4 x i16> @vld1i16(i16* %A) nounwind {
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;CHECK-LABEL: vld1i16:
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;CHECK: vld1.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
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ret <4 x i16> %tmp1
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}
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;Check for a post-increment updating load.
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define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
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;CHECK-LABEL: vld1i16_update:
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;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
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%A = load i16** %ptr
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
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%tmp2 = getelementptr i16* %A, i32 4
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store i16* %tmp2, i16** %ptr
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ret <4 x i16> %tmp1
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}
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define <2 x i32> @vld1i32(i32* %A) nounwind {
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;CHECK-LABEL: vld1i32:
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;CHECK: vld1.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
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ret <2 x i32> %tmp1
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}
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;Check for a post-increment updating load with register increment.
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define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
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;CHECK-LABEL: vld1i32_update:
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;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
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%A = load i32** %ptr
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
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%tmp2 = getelementptr i32* %A, i32 %inc
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store i32* %tmp2, i32** %ptr
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ret <2 x i32> %tmp1
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}
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define <2 x float> @vld1f(float* %A) nounwind {
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;CHECK-LABEL: vld1f:
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;CHECK: vld1.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1)
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ret <2 x float> %tmp1
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}
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define <1 x i64> @vld1i64(i64* %A) nounwind {
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;CHECK-LABEL: vld1i64:
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;CHECK: vld1.64
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1)
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ret <1 x i64> %tmp1
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}
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define <16 x i8> @vld1Qi8(i8* %A) nounwind {
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;CHECK-LABEL: vld1Qi8:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vld1.8 {d16, d17}, [r0:64]
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%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
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ret <16 x i8> %tmp1
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}
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;Check for a post-increment updating load.
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define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
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;CHECK-LABEL: vld1Qi8_update:
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;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
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%A = load i8** %ptr
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%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
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%tmp2 = getelementptr i8* %A, i32 16
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store i8* %tmp2, i8** %ptr
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ret <16 x i8> %tmp1
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}
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define <8 x i16> @vld1Qi16(i16* %A) nounwind {
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;CHECK-LABEL: vld1Qi16:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vld1.16 {d16, d17}, [r0:128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0, i32 32)
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ret <8 x i16> %tmp1
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}
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define <4 x i32> @vld1Qi32(i32* %A) nounwind {
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;CHECK-LABEL: vld1Qi32:
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;CHECK: vld1.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1)
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ret <4 x i32> %tmp1
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}
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define <4 x float> @vld1Qf(float* %A) nounwind {
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;CHECK-LABEL: vld1Qf:
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;CHECK: vld1.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1)
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ret <4 x float> %tmp1
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}
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define <2 x i64> @vld1Qi64(i64* %A) nounwind {
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;CHECK-LABEL: vld1Qi64:
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;CHECK: vld1.64
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)
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ret <2 x i64> %tmp1
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}
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declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*, i32) nounwind readonly
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declare <4 x i16> @llvm.arm.neon.vld1.v4i16(i8*, i32) nounwind readonly
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declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) nounwind readonly
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declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly
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declare <1 x i64> @llvm.arm.neon.vld1.v1i64(i8*, i32) nounwind readonly
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declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8*, i32) nounwind readonly
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declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly
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declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
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declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
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; Radar 8355607
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; Do not crash if the vld1 result is not used.
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define void @unused_vld1_result() {
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entry:
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%0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1)
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call void @llvm.trap()
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unreachable
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}
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declare void @llvm.trap() nounwind
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