mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
555 lines
18 KiB
C++
555 lines
18 KiB
C++
//===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ----=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to Hexagon assembly language. This printer is
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// the output mechanism used by `llc'.
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//
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// Documentation at http://developer.apple.com/documentation/DeveloperTools/
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// Reference/Assembler/ASMIntroduction/chapter_1_section_1.html
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "Hexagon.h"
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#include "HexagonTargetMachine.h"
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#include "HexagonSubtarget.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Module.h"
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#include "llvm/Assembly/Writer.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/Mangler.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static cl::opt<bool> AlignCalls(
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"hexagon-align-calls", cl::Hidden, cl::init(true),
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cl::desc("Insert falign after call instruction for Hexagon target"));
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namespace {
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class HexagonAsmPrinter : public AsmPrinter {
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const HexagonSubtarget *Subtarget;
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public:
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explicit HexagonAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer) {
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Subtarget = &TM.getSubtarget<HexagonSubtarget>();
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}
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virtual const char *getPassName() const {
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return "Hexagon Assembly Printer";
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}
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description. This method returns true if the
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/// machine instruction was sufficiently described to print it, otherwise it
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void printInstruction(const MachineInstr *MI, raw_ostream &O);
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virtual void EmitInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, raw_ostream &O);
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/// printRegister - Print register according to target requirements.
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///
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void printRegister(const MachineOperand &MO, bool R0AsZero,
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raw_ostream &O) {
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unsigned RegNo = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??");
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O << getRegisterName(RegNo);
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}
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void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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if (MO.isReg()) {
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printRegister(MO, false, OS);
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} else if (MO.isImm()) {
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OS << MO.getImm();
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} else {
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printOp(MO, OS);
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}
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}
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bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &OS);
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &OS);
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void printHexagonImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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int value = MI->getOperand(OpNo).getImm();
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O << value;
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}
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void printHexagonNegImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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int value = MI->getOperand(OpNo).getImm();
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O << -value;
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}
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void printHexagonMEMriOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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const MachineOperand &MO1 = MI->getOperand(OpNo);
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const MachineOperand &MO2 = MI->getOperand(OpNo+1);
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O << getRegisterName(MO1.getReg())
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<< " + #"
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<< (int) MO2.getImm();
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}
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void printHexagonFrameIndexOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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const MachineOperand &MO1 = MI->getOperand(OpNo);
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const MachineOperand &MO2 = MI->getOperand(OpNo+1);
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O << getRegisterName(MO1.getReg())
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<< ", #"
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<< MO2.getImm();
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}
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void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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// Branches can take an immediate operand. This is used by the branch
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// selection pass to print $+8, an eight byte displacement from the PC.
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if (MI->getOperand(OpNo).isImm()) {
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O << "$+" << MI->getOperand(OpNo).getImm()*4;
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} else {
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printOp(MI->getOperand(OpNo), O);
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}
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}
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void printCallOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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}
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void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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}
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void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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O << "#HI(";
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if (MI->getOperand(OpNo).isImm()) {
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printHexagonImmOperand(MI, OpNo, O);
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} else {
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printOp(MI->getOperand(OpNo), O);
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}
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O << ")";
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}
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void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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O << "#HI(";
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if (MI->getOperand(OpNo).isImm()) {
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printHexagonImmOperand(MI, OpNo, O);
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} else {
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printOp(MI->getOperand(OpNo), O);
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}
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O << ")";
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}
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void printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O);
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void printAddrModeBasePlusOffset(const MachineInstr *MI, int OpNo,
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raw_ostream &O);
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void printGlobalOperand(const MachineInstr *MI, int OpNo, raw_ostream &O);
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void printJumpTable(const MachineInstr *MI, int OpNo, raw_ostream &O);
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void EmitAlignment(unsigned NumBits, const GlobalValue *GV = 0) const;
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static const char *getRegisterName(unsigned RegNo);
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};
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} // end of anonymous namespace
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// Include the auto-generated portion of the assembly writer.
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#include "HexagonGenAsmWriter.inc"
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void HexagonAsmPrinter::EmitAlignment(unsigned NumBits,
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const GlobalValue *GV) const {
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// For basic block level alignment, use falign.
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if (!GV) {
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OutStreamer.EmitRawText(StringRef("\t.falign"));
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return;
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}
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AsmPrinter::EmitAlignment(NumBits, GV);
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}
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void HexagonAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
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switch (MO.getType()) {
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case MachineOperand::MO_Immediate:
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dbgs() << "printOp() does not handle immediate values\n";
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abort();
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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return;
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case MachineOperand::MO_JumpTableIndex:
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O << *GetJTISymbol(MO.getIndex());
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// FIXME: PIC relocation model.
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return;
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case MachineOperand::MO_ConstantPoolIndex:
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O << *GetCPISymbol(MO.getIndex());
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return;
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case MachineOperand::MO_ExternalSymbol:
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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return;
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case MachineOperand::MO_GlobalAddress: {
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// Computing the address of a global symbol, not calling it.
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O << *Mang->getSymbol(MO.getGlobal());
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printOffset(MO.getOffset(), O);
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return;
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}
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default:
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O << "<unknown operand type: " << MO.getType() << ">";
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return;
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}
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}
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//
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// isBlockOnlyReachableByFallthrough - We need to override this since the
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// default AsmPrinter does not print labels for any basic block that
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// is only reachable by a fall through. That works for all cases except
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// for the case in which the basic block is reachable by a fall through but
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// through an indirect from a jump table. In this case, the jump table
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// will contain a label not defined by AsmPrinter.
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//
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bool HexagonAsmPrinter::
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isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
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if (MBB->hasAddressTaken()) {
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return false;
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}
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return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
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}
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/// PrintAsmOperand - Print out an operand for an inline asm expression.
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///
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bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &OS) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0) return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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default: return true; // Unknown modifier.
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case 'c': // Don't print "$" before a global var name or constant.
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// Hexagon never has a prefix.
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printOperand(MI, OpNo, OS);
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return false;
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case 'L': // Write second word of DImode reference.
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// Verify that this operand has two consecutive registers.
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if (!MI->getOperand(OpNo).isReg() ||
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OpNo+1 == MI->getNumOperands() ||
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!MI->getOperand(OpNo+1).isReg())
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return true;
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++OpNo; // Return the high-part.
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break;
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case 'I':
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// Write 'i' if an integer constant, otherwise nothing. Used to print
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// addi vs add, etc.
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if (MI->getOperand(OpNo).isImm())
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OS << "i";
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return false;
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}
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}
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printOperand(MI, OpNo, OS);
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return false;
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}
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bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNo, unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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const MachineOperand &Base = MI->getOperand(OpNo);
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const MachineOperand &Offset = MI->getOperand(OpNo+1);
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if (Base.isReg())
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printOperand(MI, OpNo, O);
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else
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assert(0 && "Unimplemented");
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if (Offset.isImm()) {
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if (Offset.getImm())
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O << " + #" << Offset.getImm();
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}
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else
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assert(0 && "Unimplemented");
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return false;
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}
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void HexagonAsmPrinter::printPredicateOperand(const MachineInstr *MI,
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unsigned OpNo,
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raw_ostream &O) {
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assert(0 && "Unimplemented");
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}
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/// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to
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/// the current output stream.
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///
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void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SmallString<128> Str;
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raw_svector_ostream O(Str);
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const MachineFunction* MF = MI->getParent()->getParent();
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const HexagonMachineFunctionInfo* MFI =
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(const HexagonMachineFunctionInfo*)
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MF->getInfo<HexagonMachineFunctionInfo>();
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// Print a brace for the beginning of the packet.
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if (MFI->isStartPacket(MI)) {
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O << "\t{" << '\n';
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}
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DEBUG( O << "// MI = " << *MI << '\n';);
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// Indent
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O << "\t";
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if (MI->getOpcode() == Hexagon::ENDLOOP0) {
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if (MFI->isEndPacket(MI) && MFI->isStartPacket(MI)) {
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O << "\t{ nop }";
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} else {
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O << "}";
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}
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printInstruction(MI, O);
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} else if (MI->getOpcode() == Hexagon::STriwt) {
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//
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// Handle truncated store on Hexagon.
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//
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O << "\tmemw(";
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printHexagonMEMriOperand(MI, 0, O);
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O << ") = ";
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unsigned SubRegNum =
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TM.getRegisterInfo()->getSubReg(MI->getOperand(2)
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.getReg(), Hexagon::subreg_loreg);
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const char *SubRegName = getRegisterName(SubRegNum);
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O << SubRegName << '\n';
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} else if (MI->getOpcode() == Hexagon::MPYI_rin) {
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// Handle multipy with -ve constant on Hexagon:
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// "$dst =- mpyi($src1, #$src2)"
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printOperand(MI, 0, O);
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O << " =- mpyi(";
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printOperand(MI, 1, O);
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O << ", #";
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printHexagonNegImmOperand(MI, 2, O);
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O << ")";
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} else if (MI->getOpcode() == Hexagon::MEMw_ADDSUBi_indexed_MEM_V4) {
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//
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// Handle memw(Rs+u6:2) [+-]= #U5
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//
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O << "\tmemw("; printHexagonMEMriOperand(MI, 0, O); O << ") ";
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int addend = MI->getOperand(2).getImm();
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if (addend < 0)
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O << "-= " << "#" << -addend << '\n';
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else
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O << "+= " << "#" << addend << '\n';
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} else if (MI->getOpcode() == Hexagon::MEMw_ADDSUBi_MEM_V4) {
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//
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// Handle memw(Rs+u6:2) [+-]= #U5
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//
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O << "\tmemw("; printHexagonMEMriOperand(MI, 0, O); O << ") ";
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int addend = MI->getOperand(2).getImm();
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if (addend < 0)
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O << "-= " << "#" << -addend << '\n';
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else
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O << "+= " << "#" << addend << '\n';
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} else if (MI->getOpcode() == Hexagon::MEMh_ADDSUBi_indexed_MEM_V4) {
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//
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// Handle memh(Rs+u6:1) [+-]= #U5
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//
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O << "\tmemh("; printHexagonMEMriOperand(MI, 0, O); O << ") ";
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int addend = MI->getOperand(2).getImm();
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if (addend < 0)
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O << "-= " << "#" << -addend << '\n';
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else
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O << "+= " << "#" << addend << '\n';
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} else if (MI->getOpcode() == Hexagon::MEMh_ADDSUBi_MEM_V4) {
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//
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// Handle memh(Rs+u6:1) [+-]= #U5
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//
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O << "\tmemh("; printHexagonMEMriOperand(MI, 0, O); O << ") ";
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int addend = MI->getOperand(2).getImm();
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if (addend < 0)
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O << "-= " << "#" << -addend << '\n';
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else
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O << "+= " << "#" << addend << '\n';
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} else if (MI->getOpcode() == Hexagon::MEMb_ADDSUBi_indexed_MEM_V4) {
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//
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// Handle memb(Rs+u6:1) [+-]= #U5
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//
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O << "\tmemb("; printHexagonMEMriOperand(MI, 0, O); O << ") ";
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int addend = MI->getOperand(2).getImm();
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if (addend < 0)
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O << "-= " << "#" << -addend << '\n';
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else
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O << "+= " << "#" << addend << '\n';
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} else if (MI->getOpcode() == Hexagon::MEMb_ADDSUBi_MEM_V4) {
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//
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// Handle memb(Rs+u6:1) [+-]= #U5
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//
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O << "\tmemb("; printHexagonMEMriOperand(MI, 0, O); O << ") ";
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int addend = MI->getOperand(2).getImm();
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if (addend < 0)
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O << "-= " << "#" << -addend << '\n';
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else
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O << "+= " << "#" << addend << '\n';
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} else if (MI->getOpcode() == Hexagon::CMPbGTri_V4) {
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//
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// Handle Pd=cmpb.gt(Rs,#s8)
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//
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O << "\t";
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printRegister(MI->getOperand(0), false, O);
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O << " = cmpb.gt(";
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printRegister(MI->getOperand(1), false, O);
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O << ", ";
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int val = MI->getOperand(2).getImm() >> 24;
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O << "#" << val << ")" << '\n';
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} else if (MI->getOpcode() == Hexagon::CMPhEQri_V4) {
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//
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// Handle Pd=cmph.eq(Rs,#8)
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//
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O << "\t";
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printRegister(MI->getOperand(0), false, O);
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O << " = cmph.eq(";
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printRegister(MI->getOperand(1), false, O);
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O << ", ";
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int val = MI->getOperand(2).getImm();
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assert((((0 <= val) && (val <= 127)) ||
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((65408 <= val) && (val <= 65535))) &&
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"Not in correct range!");
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if (val >= 65408) val -= 65536;
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O << "#" << val << ")" << '\n';
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} else if (MI->getOpcode() == Hexagon::CMPhGTri_V4) {
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//
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// Handle Pd=cmph.gt(Rs,#8)
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//
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O << "\t";
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|
printRegister(MI->getOperand(0), false, O);
|
|
O << " = cmph.gt(";
|
|
printRegister(MI->getOperand(1), false, O);
|
|
O << ", ";
|
|
int val = MI->getOperand(2).getImm() >> 16;
|
|
O << "#" << val << ")" << '\n';
|
|
} else {
|
|
printInstruction(MI, O);
|
|
}
|
|
|
|
// Print a brace for the end of the packet.
|
|
if (MFI->isEndPacket(MI) && MI->getOpcode() != Hexagon::ENDLOOP0) {
|
|
O << "\n\t}" << '\n';
|
|
}
|
|
|
|
if (AlignCalls && MI->getDesc().isCall()) {
|
|
O << "\n\t.falign" << "\n";
|
|
}
|
|
|
|
OutStreamer.EmitRawText(O.str());
|
|
return;
|
|
}
|
|
|
|
/// PrintUnmangledNameSafely - Print out the printable characters in the name.
|
|
/// Don't print things like \n or \0.
|
|
// static void PrintUnmangledNameSafely(const Value *V, raw_ostream &OS) {
|
|
// for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen();
|
|
// Name != E; ++Name)
|
|
// if (isprint(*Name))
|
|
// OS << *Name;
|
|
// }
|
|
|
|
|
|
void HexagonAsmPrinter::printAddrModeBasePlusOffset(const MachineInstr *MI,
|
|
int OpNo, raw_ostream &O) {
|
|
const MachineOperand &MO1 = MI->getOperand(OpNo);
|
|
const MachineOperand &MO2 = MI->getOperand(OpNo+1);
|
|
|
|
O << getRegisterName(MO1.getReg())
|
|
<< " + #"
|
|
<< MO2.getImm();
|
|
}
|
|
|
|
|
|
void HexagonAsmPrinter::printGlobalOperand(const MachineInstr *MI, int OpNo,
|
|
raw_ostream &O) {
|
|
const MachineOperand &MO = MI->getOperand(OpNo);
|
|
assert( (MO.getType() == MachineOperand::MO_GlobalAddress) &&
|
|
"Expecting global address");
|
|
|
|
O << *Mang->getSymbol(MO.getGlobal());
|
|
if (MO.getOffset() != 0) {
|
|
O << " + ";
|
|
O << MO.getOffset();
|
|
}
|
|
}
|
|
|
|
void HexagonAsmPrinter::printJumpTable(const MachineInstr *MI, int OpNo,
|
|
raw_ostream &O) {
|
|
const MachineOperand &MO = MI->getOperand(OpNo);
|
|
assert( (MO.getType() == MachineOperand::MO_JumpTableIndex) &&
|
|
"Expecting jump table index");
|
|
|
|
// Hexagon_TODO: Do we need name mangling?
|
|
O << *GetJTISymbol(MO.getIndex());
|
|
}
|
|
|
|
extern "C" void LLVMInitializeHexagonAsmPrinter() {
|
|
RegisterAsmPrinter<HexagonAsmPrinter> X(TheHexagonTarget);
|
|
}
|